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| mixed signal isp flash mcu family c8051f360/1/2/3/4/5/6/7/8/9 rev. 1.0 7/07 copyright ? 2007 by silicon laboratories c8051f36x this information applies to a product under development. its characteristics and specifications are subject to change without n otice. analog peripherals - 10-bit adc (?f360/1/2/6/7/8/9 only) ? up to 200 ksps ? up to 21 external single-ended or differential inputs ? vref from internal vref, external pin or v dd ? internal or external start of conversion source ? built-in temperature sensor - 10-bit current output dac (?f360/1/2/6/7/8/9 only) - two comparators ? programmable hysteresis and response time ? configurable as interrupt or reset source ? low current (0.4 a) - brown-out detector and por circuitry on-chip debug - on-chip debug circuitry facilitates full speed, non- intrusive in-system debug (no emulator required) - provides breakpoints, single stepping, inspect/modify memory and registers - superior performance to emulation systems using ice-chips, target pods, and sockets - low cost, complete development kit supply voltage - range: 2.7?3.6 v (50 mi ps) 3.0?3.6 v (100 mips) - power saving suspend and shutdown modes high speed 8051 c core - pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks - 100 mips or 50 mips throughput with on-chip pll - expanded interrupt handler - 2-cycle 16 x 16 mac engine memory - 1280 bytes internal data ram (256 + 1024) - 32 kb (?f360/1/2/ 3/4/5/6/7) or 16 kb (?f368/9) flash; in-system prog rammable in 1024-byte sectors? 1024 bytes are reserved in the 32 kb devices digital peripherals - up to 39 port i/o; all 5 v tolerant with high sink cur - rent - hardware enhanced uart, smbus?, and enhanced spi? serial ports - four general purpose 16-bit counter/timers - 16-bit programmable coun ter array (pca) with six capture/compare modules - real time clock mode using pca or timer and exter - nal clock source - external memory interface (emif) clock sources - two internal oscillators: ? 24.5 mhz with 2% accuracy suppor ts crystal-less uart operation ? 80/40/20/10 khz low frequency, low power - flexible pll technology - external oscillator: crystal, rc, c, or clock (1 or 2 pin modes) - can switch between clock s ources on-the-fly; useful in power saving modes packages - 48-pin tqfp (c8051f360/3) - 32-pin lqfp (c8051f361/4/6/8) - 28-pin qfn (c8051f362/5/7/9) temperature range: ?40 to +85 c analog peripherals 32/16 kb isp flash 1024 b sram por debug circuitry flexible interrupts 8051 cpu (100 or 50 mips) digital i/o high-speed controller core crossbar wdt port 0 port 1 port 2 external memory interface port 4 port 3 port 3 48-pin only 16 x 16 mac internal oscillator/ lfo/pll uart smbus pca timer 0 timer 1 timer 2 timer 3 spi a m u x 10-bit 200 ksps adc temp sensor 10-bit current dac ?f360/1/2/6/7/8/9 only voltage comparators + - + -
c8051f360/1/2/3/4/5/6/7/8/9 2 rev. 1.0 rev. 1.0 3 c8051f360/1/2/3/4/5/6/7/8/9 table of contents 1. system overview............ ............................................................................. ........... 18 1.1. cip-51? microcontroller core.. ............................................................. ........... 22 1.1.1. fully 8051 compatible...... ............................................................. ........... 22 1.1.2. improved throughput ............ ........................................................ ........... 22 1.1.3. additional features .......... ............................................................. ........... 23 1.2. on-chip memory......... ........................................................................... ........... 24 1.3. on-chip debug circuitr y.................... .................................................. ............. 24 1.4. programmable digital i/o and crossbar ............... ................................. ........... 25 1.5. serial ports ............ ................................................................................ ........... 26 1.6. programmable counter array ... ............................................................. ........... 26 1.7. 10-bit analog to digital conver ter.................... .............. ............... ........... ......... 27 1.8. comparators .......................................................................................... ........... 28 1.9. 10-bit current output dac...... ............................................................... ........... 30 2. absolute maximum ratings ........ ............................................................... ........... 32 3. global electrical characteristic s .................. ............................................. ........... 33 4. pinout and package definitions..... ............... ............................................. ........... 36 5. 10-bit adc (adc 0, c8051f360/1/2/6/7/8/9)... ............................................. ........... 47 5.1. analog multiplexer ...... ........................................................................... ........... 48 5.2. temperature sensor ............ .................................................................. ........... 49 5.3. modes of operation ............. .................................................................. ........... 51 5.3.1. starting a conversion....... ............................................................. ........... 51 5.3.2. tracking modes................ ............................................................. ........... 52 5.3.3. settling time r equirements ................ .......................................... ........... 53 5.4. programmable window detector ........................................................... ........... 58 5.4.1. window detector in sing le-ended mode .......... ............................ ........... 60 5.4.2. window detector in differential mode..... .............. ............... ........... ......... 61 6. 10-bit current mode dac (ida 0, c8051f360/1/2/6/7/8/9) ...... ................. ............. 63 6.1. ida0 output scheduling . ................. ........................................................ ......... 63 6.1.1. update output on-demand .. ........................................................ ........... 63 6.1.2. update output based on timer overflow ............. ............... ........... ......... 64 6.1.3. update output based on cnvstr edge................... ................. ............. 64 6.2. idac output mapping.......... .................................................................. ........... 64 7. voltage reference (c8051f360/1/2/6/7/8/9) ....... .......................................... ......... 67 8. comparators ................ ................................................................................ ........... 70 9. cip-51 microcontroller ........... .................................................................. ............. 80 9.1. performance .......................................................................................... ........... 80 9.2. programming and debugging suppor t ................................................ ............. 81 9.3. instruction set ........... ............................................................................. ........... 82 9.3.1. instruction and cpu timing .. ........................................................ ........... 82 9.3.2. movx instruction and program memory ... ................................. ............. 82 9.4. memory organization........... .................................................................. ........... 86 9.4.1. program memory.............. ............................................................. ........... 86 9.4.2. data memory........ ......................................................................... ........... 87 c8051f360/1/2/3/4/5/6/7/8/9 4 rev. 1.0 9.4.3. general purpose registers ........................................................... ........... 87 9.4.4. bit addressable lo cations.............. ............................................... ........... 87 9.4.5. stack ................. ........................................................................... ........... 87 9.4.6. special function registers. ........................................................... ........... 88 9.4.7. register descriptions ....... ............................................................. ......... 102 9.5. power management modes ........... ........................................................ ......... 104 9.5.1. idle mode............ ........................................................................... ......... 105 9.5.2. stop mode ...................... ............................................................... ......... 105 9.5.3. suspend mode ................. ............................................................. ......... 105 10. interrupt handler ............ ............................................................................. ......... 107 10.1.mcu interrupt source s and vectors.............. ................................................. 107 10.2.interrupt priorities ..... ............................................................................. ......... 108 10.3.interrupt latency....... ............................................................................. ......... 108 10.4.interrupt register de scriptions ............. ................................................. ......... 109 10.5.external interrupts .... ............................................................................. ......... 115 11. multiply and accumulate (mac0) ............... ............................................... ......... 117 11.1.special function registers..... ............................................................... ......... 117 11.2.integer and fractional math.... ............................................................... ......... 118 11.3.operating in multiply and accumulate mode .. ................................................ 119 11.4.operating in multiply only mode ........................................................... ......... 119 11.5.accumulator shift operations.. ............... ............................................... ......... 119 11.6.rounding and saturation.......... ............................................................. ......... 120 11.7.usage examples .......... ......................................................................... ......... 120 11.7.1.multiply and accumulate example ............... ................................. ......... 120 11.7.2.multiply only example...... ............................................................. ......... 121 11.7.3.mac0 accumulator shift example ............... ................................. ......... 121 12. reset sources.......... .................................................................................. ........... 128 12.1.power-on reset ....... ............................................................................. ......... 129 12.2.power-fail reset/vdd monitor ............ ................................................. ......... 130 12.3.external reset .......... ............................................................................. ......... 131 12.4.missing clock detector reset ... ............... ............................................. ......... 131 12.5.comparator0 reset ............. .................................................................. ......... 131 12.6.pca watchdog timer reset ..... ............... ............................................. ......... 132 12.7.flash error reset ..... ............................................................................. ......... 132 12.8.software reset ......... ............................................................................. ......... 132 13. flash memory ................. ............................................................................. ......... 135 13.1.programming the flash memory ........................................................... ......... 135 13.1.1.flash lock and key functi ons ................ .............. ............... .................. 135 13.1.2.erasing flash pages from software ........... ................................. ......... 136 13.1.3.writing flash memory from software.......... ................................. ......... 136 13.1.4.non-volatile data storage . ............... ............................................. ......... 137 13.2.security options ....... ............................................................................. ......... 138 13.2.1.summary of flash security options............. ................................. ......... 139 13.3.flash write and erase guidelines ............... .......................................... ......... 140 13.3.1.vdd maintenance and the vd d monitor .......... ............................ ......... 140 rev. 1.0 5 c8051f360/1/2/3/4/5/6/7/8/9 13.3.2.16.4.2 pswe maintenance ... ........................................................ ......... 141 13.3.3.system clock ....... ......................................................................... ......... 141 13.4.flash read timing ....... ......................................................................... ......... 143 14. branch target cache .............. .................................................................. ........... 145 14.1.cache and prefetch operation . ............................................................. ......... 145 14.2.cache and prefetch optimizati on................ .......................................... ......... 146 15. external data memory interface and on-chi p xram............ ................. ........... 153 15.1.accessing xram.......... ......................................................................... ......... 153 15.1.1.16-bit movx example ....... ........................................................... ......... 153 15.1.2.8-bit movx example ......... ........................................................... ......... 153 15.2.configuring the exte rnal memory interface . .......................................... ......... 154 15.3.port configuration..... ............................................................................. ......... 154 15.4.multiplexed and non-multiplex ed selection.......... ................................. ......... 157 15.4.1.multiplexed configuration. ............................................................. ......... 157 15.4.2.non-multiplexed configurat ion.............. ................................................. 158 15.5.memory mode selection...... .................................................................. ......... 159 15.5.1.internal xram only ......... ............................................................. ......... 159 15.5.2.split mode without bank select ............. ................................................. 159 15.5.3.split mode with ba nk select................ .......................................... ......... 160 15.5.4.external only...... ........................................................................... ......... 160 15.6.timing ............. .................................................................................. ........... 160 15.6.1.non-multiplexed mode ....... ........................................................... ......... 162 15.6.2.multiplexed mode .... ...................................................................... ......... 165 16. oscillators ................ .................................................................................. ........... 169 16.1.programmable internal hi gh-frequency (h-f) oscillator ... ................. ........... 169 16.1.1. internal oscillator sus pend mode ............... ................................. ......... 170 16.2.programmable internal low -frequency (l-f) oscillator .... ................. ........... 171 16.2.1.calibrating the internal l- f oscillator........... ................................. ......... 172 16.3.external oscillator drive circuit................ ............................................. ......... 173 16.4.system clock selectio n......................................................................... ......... 173 16.5.external crystal example .... .................................................................. ......... 176 16.6.external rc example .......... .................................................................. ......... 177 16.7.external capacitor example ... ............................................................... ......... 177 16.8.phase-locked loop (pll).......... ........................................................... ......... 178 16.8.1.pll input clock and pre-divi der ................................................... ......... 178 16.8.2.pll multiplication and ou tput clock ............ ................................. ......... 178 16.8.3.powering on and initializing the pll .............. ............................... ......... 179 17. port input/output............ ............................................................................. ......... 183 17.1.priority crossbar decoder ... .................................................................. ......... 185 17.2.port i/o initialization ........ ...................................................................... ......... 187 17.3.general purpose port i/o .... .................................................................. ......... 190 18. smbus ................. ......................................................................................... ......... 202 18.1.supporting documents ............. ............................................................. ......... 203 18.2.smbus configuration... ............... ........................................................... ......... 203 c8051f360/1/2/3/4/5/6/7/8/9 6 rev. 1.0 18.3.smbus operation ....... ........................................................................... ......... 203 18.3.1.arbitration......... ............................................................................. ......... 204 18.3.2.clock low extension........ ............................................................. ......... 204 18.3.3.scl low timeout.... ...................................................................... ......... 204 18.3.4.scl high (smbus free) ti meout .............. ................................. ........... 205 18.4.using the smbus........ ........................................................................... ......... 205 18.4.1.smbus configuration regist er................ .............. ............... .................. 206 18.4.2.smb0cn control register . ........................................................... ......... 209 18.4.3.data register ....... ......................................................................... ......... 212 18.5.smbus transfer modes... ...................................................................... ......... 213 18.5.1.master transmitter mode .. ............... ............................................. ......... 213 18.5.2.master receiver mode .............. .................................................. ........... 214 18.5.3.slave receiver mode ....... ............................................................. ......... 215 18.5.4.slave transmitter mode .... ............... ............................................. ......... 216 18.6.smbus status decoding ........................................................................ ......... 217 19. uart0................ ........................................................................................... ......... 220 19.1.enhanced baud rate g eneration.................. ................................................. 221 19.2.operational modes ....... ......................................................................... ......... 222 19.2.1.8-bit uart ........... ......................................................................... ......... 222 19.2.2.9-bit uart ........... ......................................................................... ......... 223 19.3.multiprocessor communications ... ........................................................ ......... 224 20. enhanced serial peripheral interface (spi0)..... ................................................. 234 20.1.signal descriptions....... ......................................................................... ......... 235 20.1.1.master out, slave in (mos i)...................... ................................. ........... 235 20.1.2.master in, slave out (miso)............... .......................................... ......... 235 20.1.3.serial clock (sck) ........... ............................................................. ......... 235 20.1.4.slave select (nss) .......... ............................................................. ......... 235 20.2.spi0 master mode operation . ............................................................... ......... 236 20.3.spi0 slave mode operation ..... ............................................................. ......... 238 20.4.spi0 interrupt sources ........ .................................................................. ......... 238 20.5.serial clock timing... ............................................................................. ......... 239 20.6.spi special function registers . ............... ............................................. ......... 241 21. timers................ ............................................................ ............... .............. ........... 24 7 21.1.t imer 0 and ti mer 1 ............... ............................................................... ......... 248 21.1.1.mode 0: 13-bit counter/timer ................. .............. ............... .................. 248 21.1.2.mode 1: 16-bit counter/timer ................. .............. ............... .................. 249 21.1.3.mode 2: 8-bit counter/tim er with auto-reload.......... ................. ........... 249 21.1.4.mode 3: two 8-bit counter /timers (timer 0 only)..... ................. ........... 251 21.2.timer 2 ............. .................................................................................. ........... 256 21.2.1.16-bit timer with auto-rel oad............... ................................................. 256 21.2.2.8-bit timers with auto-rel oad............... ................................................. 257 21.3.timer 3 ............. .................................................................................. ........... 260 21.3.1.16-bit timer with auto-rel oad............... ................................................. 260 21.3.2.8-bit timers with auto-rel oad............... ................................................. 261 rev. 1.0 7 c8051f360/1/2/3/4/5/6/7/8/9 22. programmable counter array ....... ............................................................. ......... 264 22.1.pca counter/timer ............. .................................................................. ......... 265 22.2.capture/compare modules ...... ............................................................. ......... 266 22.2.1.edge-triggered captur e mode................. .............. ............... .................. 267 22.2.2.software timer (compare) mode................. ................................. ......... 268 22.2.3.high speed output mode.............................................................. ......... 269 22.2.4.frequency output mode ....... ........................................................ ......... 270 22.2.5.8-bit pulse width modulato r mode............... ................................. ......... 271 22.2.6.16-bit pulse width modulat or mode............. ................................. ......... 272 22.3.watchdog timer mode .... ...................................................................... ......... 272 22.3.1.watchdog timer operation ... ........................................................ ......... 273 22.3.2.watchdog timer usage ........ ........................................................ ......... 274 22.4.register descriptions for pca0 ............................................................. ......... 276 23. revision specific behavior ......... ............................................................... ......... 281 23.1.revision identification.......... .................................................................. ......... 281 23.2.c2d port pin requirements ..... ............................................................. ......... 283 24. c2 interface ................ .................................................................................. ......... 284 24.1.c2 interface registers......... .................................................................. ......... 284 24.2.c2 pin sharing ......... ............................................................................. ......... 286 document change list .... ................................................................................ ......... 287 contact information ......... ................................................................................ ......... 288 c8051f360/1/2/3/4/5/6/7/8/9 8 rev. 1.0 list of figures 1. system overview figure 1.1. c8051f360/3 block diagram ................ .............. ............... ........... ......... 20 figure 1.2. c8051f361/4/6/8 block di agram ............... ................................. ........... 21 figure 1.3. c8051f362/5/7/9 block di agram ............... ................................. ........... 21 figure 1.4. comparison of peak mcu executio n speeds ......... ................. ............. 22 figure 1.5. on-chip clock and rese t .............. ............................................. ...........23 figure 1.6. on-board memory map .. ............... ............................................. ........... 24 figure 1.7. development/in-syst em debug diagram .... ............................... ........... 25 figure 1.8. digital crossbar diagr am (port 0 to port 3) ............. ................. ............. 26 figure 1.9. pca block diagram ..... ............................................................... ........... 27 figure 1.10. pca block diagram ..... ............................................................. ...........27 figure 1.11. 10-bit adc bl ock diagram ....... ................................................. ........... 28 figure 1.12. comparator0 block di agram ........... .......................................... ........... 29 figure 1.13. comparator1 block di agram ........... .......................................... ........... 30 figure 1.14. ida0 functional blo ck diagram ............. ................................. ............. 31 2. absolute maximum ratings 3. global electrical characteristics 4. pinout and package definitions figure 4.1. tqfp-48 pinout diagram (top view) ... .............. ............... ........... ......... 39 figure 4.2. tqfp-48 pack age diagram .............. .......................................... ........... 40 figure 4.3. lqfp-32 pinout diagram (top view) ... .............. ............... ........... ......... 41 figure 4.4. lqfp-32 pack age diagram .............. .......................................... ........... 42 figure 4.5. qfn-28 pinout diagram (top view) .......... ................................. ........... 43 figure 4.6. qfn-28 package drawi ng ................ .......................................... ........... 44 figure 4.7. typical qfn-28 landing diagram ............. ................................. ........... 45 figure 4.8. qfn-28 solder past e recommendation ................. ................. ............. 46 5. 10-bit adc (adc0, c8051f360/1/2/6/7/8/9) figure 5.1. adc0 functi onal block diagram ...... .......................................... ........... 47 figure 5.2. typical temperature sensor transfer function .... ............ ........... ......... 49 figure 5.3. temperature sensor error with 1-po int calibration ........ .............. ......... 50 figure 5.4. 10-bit adc track and conversion example timing ................. ............. 52 figure 5.5. adc0 equival ent input circuits ...... ............................................. ........... 53 figure 5.6. adc window compar e example: right-justified single-ended data ... 60 figure 5.7. adc window compar e example: left-justified si ngle-ended data ..... 60 figure 5.8. adc window compar e example: right-justified differential data ....... 61 figure 5.9. adc window compar e example: left-justified dif ferential data .......... 61 6. 10-bit current mode dac (ida0, c8051f360/1/2/6/7/8/9) figure 6.1. ida0 functional block diagram ............... ................................. ............. 63 figure 6.2. ida0 data word mappi ng ................. .......................................... ...........64 7. voltage reference (c8051f360/1/2/6/7/8/9) figure 7.1. voltage reference f unctional block diagram ......... ................. ............. 67 8. comparators figure 8.1. comparator0 functional block diagram .... ................................. ........... 70 rev. 1.0 9 c8051f360/1/2/3/4/5/6/7/8/9 figure 8.2. comparator1 functional block diagram ............... ............ ........... ......... 71 figure 8.3. comparator hysteresis plot ................. .............. ............... ........... ......... 72 9. cip-51 microcontroller figure 9.1. cip-51 bl ock diagram ......... ........................................................ ......... 81 figure 9.2. memory map .. ................. ........................................................... ........... 86 figure 9.3. sfr page stack ....... .................................................................. ........... 89 figure 9.4. sfr page sta ck while using sfr page 0x0f to access oscicn .... 90 figure 9.5. sfr page stack after adc0 window comparator interrupt occurs .... 91 figure 9.6. sfr page stack upon pca interrupt occurri ng during an adc0 isr . 91 figure 9.7. sfr page stack upon return from pca interrupt ................. ............. 92 figure 9.8. sfr page stack upon return from ad c2 window interrupt .............. 93 10. interrupt handler 11. multiply and accumulate (mac0) figure 11.1. mac0 block diagram ............................................................... ......... 117 figure 11.2. integer mo de data representation .......................................... ......... 118 figure 11.3. fracti onal mode data representation .......... ............................ ......... 118 figure 11.4. mac0 pipeline ............... ........................................................... ......... 119 12. reset sources figure 12.1. rese t sources ............. ............................................................. ......... 128 figure 12.2. power-on and vdd monitor re set timing ...... ............... .................. 129 13. flash memory figure 13.1. flash program memo ry map .......... .......................................... ......... 138 14. branch target cache figure 14.1. branch target cache data flow .... .......................................... ......... 145 figure 14.2. branch tar get cache organization .. ................................................. 146 figure 14.3. cache lock oper ation ............... ............................................... ......... 148 15. external data memory interface and on-chip xram figure 15.1. multiplex ed configuration example .......................................... ......... 157 figure 15.2. non-multip lexed configuration example ........ ................................... 158 figure 15.3. emif operating modes ............. ............................................... ......... 159 figure 15.4. non-multip lexed 16-bit movx timing .............. ............... .................. 162 figure 15.5. non-multiplexed 8-bit movx without bank sele ct timing ................ 163 figure 15.6. non-multiplexed 8-bit movx with bank select timing .......... ........... 164 figure 15.7. multiplexed 16-bit movx timing ........... ................................. ........... 165 figure 15.8. multiplexed 8-bit movx without bank select ti ming ............. ........... 166 figure 15.9. multiplexed 8-bit movx with bank select timing ............................. 167 16. oscillators figure 16.1. oscillator diagram .............. ............................................................... 169 figure 16.2. 32.768 khz external crystal example ..... ................................. ......... 176 figure 16.3. pll block dia gram ........... ........................................................ ......... 178 17. port input/output figure 17.1. port i/o functional block diagram (port 0 through port 3) ............... 183 figure 17.2. port i/o ce ll block diagram ........ ............................................. ......... 184 figure 17.3. crossbar priority decoder with no pins sk ipped ................ .............. 185 figure 17.4. crossbar priority decoder with port pins skipped ............ ................ 186 c8051f360/1/2/3/4/5/6/7/8/9 10 rev. 1.0 18. smbus figure 18.1. smbus block diagram ............ ................................................. ......... 202 figure 18.2. typical smbu s configuration ......... .......................................... ......... 203 figure 18.3. smbus transaction ..... ............................................................. ......... 204 figure 18.4. typical sm bus scl generation ....... ................................................. 207 figure 18.5. typical ma ster transmitter sequence ............ ................................... 213 figure 18.6. typical ma ster receiver sequence ................ ................................... 214 figure 18.7. typical slave rece iver sequence ........... ................................. ......... 215 figure 18.8. typical slave trans mitter sequence ....... ................................. ......... 216 19. uart0 figure 19.1. uart0 block diagram ............ ................................................. ......... 220 figure 19.2. uart0 baud rate logic ........... ............................................... ......... 221 figure 19.3. uart interconnect di agram ............ ................................................. 222 figure 19.4. 8-bit uart timing diagram ........... .......................................... ......... 222 figure 19.5. 9-bit uart timing diagram ........... .......................................... ......... 223 figure 19.6. uart multi-proc essor mode interconne ct diagram ......... ................ 224 20. enhanced serial peripheral interface (spi0) figure 20.1. spi blo ck diagram ........... ........................................................ ......... 234 figure 20.2. multiple-m aster mode connection di agram ................. ..................... 237 figure 20.3. 3- wire single master and 3- wire single slave mode connection diagram ............ .................................................. ........... 237 figure 20.4. 4-wi re single master mode and 4-wire slave mode connection diagram ............ .................................................. ........... 237 figure 20.5. master mode data/ clock timing ............. ................................. ......... 239 figure 20.6. slave mode data/clock timing (ckpha = 0) .. ............... .................. 240 figure 20.7. slave mode data/clock timing (ckpha = 1) .. ............... .................. 240 figure 20.8. spi ma ster timing (ckpha = 0) ............... ............................... ......... 244 figure 20.9. spi ma ster timing (ckpha = 1) ............... ............................... ......... 244 figure 20.10. spi slave timing (c kpha = 0) ............. ................................. ......... 245 figure 20.11. spi slave timing (c kpha = 1) ............. ................................. ......... 245 21. timers figure 21.1. t0 mode 0 bl ock diagram .............. .......................................... ......... 249 figure 21.2. t0 mode 2 bl ock diagram .............. .......................................... ......... 250 figure 21.3. t0 mode 3 bl ock diagram .............. .......................................... ......... 251 figure 21.4. timer 2 16- bit mode block diagram ................................................. 256 figure 21.5. timer 2 8- bit mode block diagram .......................................... ......... 257 figure 21.6. timer 3 16- bit mode block diagram ................................................. 260 figure 21.7. timer 3 8- bit mode block diagram .......................................... ......... 261 22. programmable counter array figure 22.1. pca block diagram ... ............................................................... ......... 264 figure 22.2. pca counter /timer block diagram .. ................................................. 265 figure 22.3. pca interrupt block diagr am ................ ................................. ........... 266 figure 22.4. pca captur e mode diagram ............ ................................................. 267 figure 22.5. pca software time r mode diagram ....... ................................. ......... 268 figure 22.6. pca high speed output mode diagram ............... ................. ........... 269 rev. 1.0 11 c8051f360/1/2/3/4/5/6/7/8/9 figure 22.7. pca fr equency output mode ........ .......................................... ......... 270 figure 22.8. pca 8-bit pwm mode diagram ......... .............. ............... .................. 271 figure 22.9. pca 16-bit pwm mode ............... ............................................. ......... 272 figure 22.10. pca module 5 wi th watchdog timer enabled .... ................. ........... 273 23. revision specific behavior figure 23.1. device package - tqfp 48 ......... ............................................. ......... 281 figure 23.2. device package - lqfp 32 ......... ............................................. ......... 282 figure 23.3. device package - qfn 28 ........... ............................................. ......... 282 24. c2 interface figure 24.1. typical c2 pin sharing ......... .................................................. ........... 286 c8051f360/1/2/3/4/5/6/7/8/9 12 rev. 1.0 list of tables 1. system overview table 1.1. product select ion guide ................. ............................................. ........... 19 2. absolute maximum ratings table 2.1. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3. global electrical characteristics table 3.1. global electric al characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 3.2. index to electrical characteristics tables .................... ................ ........... 35 4. pinout and package definitions table 4.1. pin definitions for t he c8051f36x ............ ................................. ............. 36 table 4.2. tqfp-48 package dime nsions ................ ................................. ............. 40 table 4.3. lqfp-32 package dime nsions ................ ................................. ............. 42 table 4.4. qfn-28 package dimensions ........... .......................................... ........... 44 5. 10-bit adc ( adc0, c8051f360/1/2/6/7/8/9) table 5.1. adc0 elec trical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6. 10-bit current mode dac (i da0, c8051f360/1/2/6/7/8/9) table 6.1. idac electrical characte ristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 7. voltage reference (c8051f360/1/2/6/7/8/9) table 7.1. voltage reference electr ical characteristics . . . . . . . . . . . . . . . . . . . . . 69 8. comparators table 8.1. comparator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 79 9. cip-51 microcontroller table 9.1. cip-51 instruction se t summary .............. ................................. ............. 82 table 9.2. special function regi ster (sfr) memory map ...... ............ ........... ......... 96 table 9.3. special functi on registers ................ .......................................... ........... 97 10. interrupt handler table 10.1. interrupt summ ary ................. .................................................. ........... 108 11. multiply and accumulate (mac0) table 11.1. mac0 rounding (mac0sa t = 0) ............. ................................. ......... 120 12. reset sources table 12.1. reset electrical charac teristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 13. flash memory table 13.1. flash security summar y ................. .......................................... ......... 139 table 13.2. flash electrical char acteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 14. branch target cache 15. external data memory interface and on-chip xram table 15.1. emif pinout (c8051f3 60/3) ............ .......................................... ......... 155 table 15.2. ac parameters for external memory interface ..... ............ .................. 168 16. oscillators table 16.1. internal hig h frequency oscillator electrical characteristics . . . . . . . 171 table 16.2. internal low frequency oscillator electrical char acteristics . . . . . . . 172 table 16.3. pll frequency c haracteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 table 16.4. pll lock timi ng characteristics ....... ................................................. 182 rev. 1.0 13 c8051f360/1/2/3/4/5/6/7/8/9 17. port input/output table 17.1. port i/o dc el ectrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 201 18. smbus table 18.1. smbus clock source selection .............. ................................. ........... 206 table 18.2. minimum sda setup and hold times ...... ................................. ......... 207 table 18.3. sources for hardwa re changes to smb0cn ......... ................. ........... 211 table 18.4. smbus status decoding ............... ............................................. ......... 217 19. uart0 table 19.1. timer settings for standard baud rates using the internal 24.5 mhz oscillator ......... ............................ ......... 227 table 19.2. timer settings for standard baud rates using an external 25.0 mhz oscillator .......... ............................ ......... 228 table 19.3. timer settings for standard baud rates using an external 22.1184 mh z oscillator .... ............................ ......... 229 table 19.4. timer settings for standard baud rates using an external 18.432 mhz oscillator ...... ............................ ......... 230 table 19.5. timer settings for standard baud rates using an external 11.0592 mh z oscillator .... ............................ ......... 231 table 19.6. timer settings for standard baud rates using an external 3.6864 mhz oscillator ...... ............................ ......... 232 table 19.7. timer settings fo r standard baud rates using th e pll ......... ........... 233 table 19.8. timer settings fo r standard baud rates using th e pll ......... ........... 233 20. enhanced serial peripheral interface (spi0) table 20.1. spi slave timing para meters ......... .......................................... ......... 246 21. timers 22. programmable counter array table 22.1. pca timebase input op tions ............ ................................................. 265 table 22.2. pca0cpm register settings for pca captur e/compare modules .... 267 table 22.3. watchdog timer timeout intervals ........... ................................. ......... 275 23. revision specific behavior 24. c2 interface c8051f360/1/2/3/4/5/6/7/8/9 14 rev. 1.0 list of registers sfr definition 5.1. amx0p: amux0 positive channel select . . . . . . . . . . . . . . . . . . . 54 sfr definition 5.2. amx0n: amux 0 negative channel select . . . . . . . . . . . . . . . . . . 55 sfr definition 5.3. adc0cf: adc0 c onfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 sfr definition 5.4. adc0h: adc0 data word msb . . . . . . . . . . . . . . . . . . . . . . . . . . 56 sfr definition 5.5. adc0l: adc0 data word lsb . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 sfr definition 5.6. adc0cn: adc0 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 sfr definition 5.7. adc0gth: a dc0 greater-than data high byte . . . . . . . . . . . . . 58 sfr definition 5.8. a dc0gtl: adc0 greater-than data low byte . . . . . . . . . . . . . . 58 sfr definition 5.9. adc0lth: ad c0 less-than data high byte . . . . . . . . . . . . . . . . 59 sfr definition 5.10. adc0ltl: ad c0 less-than data low byte . . . . . . . . . . . . . . . . 59 sfr definition 6.1. ida0cn: ida0 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 sfr definition 6.2. ida0h: ida0 da ta word msb . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 sfr definition 6.3. ida0l: ida0 data word lsb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 sfr definition 7.1. ref0cn: reference control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 sfr definition 8.1. cpt0cn : comparator0 control . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 sfr definition 8.2. cpt0mx : comparator0 mux select ion . . . . . . . . . . . . . . . . . . . . 74 sfr definition 8.3. cpt0md : comparator0 mode selection . . . . . . . . . . . . . . . . . . . . 75 sfr definition 8.4. cpt1cn : comparator1 control . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 sfr definition 8.5. cpt1mx : comparator1 mux select ion . . . . . . . . . . . . . . . . . . . . 77 sfr definition 8.6. cpt1md : comparator1 mode selection . . . . . . . . . . . . . . . . . . . . 78 sfr definition 9.1. sfr0cn: sfr page control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 sfr definition 9.2. sfrpage: sfr page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 sfr definition 9.3. sfrnext: sfr next register . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 sfr definition 9.4. sfrlast: sfr las t register . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 sfr definition 9.5. sp: stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 sfr definition 9.6. dpl: da ta pointer low byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 sfr definition 9.7. dph: data pointer high byte . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 sfr definition 9.8. psw: pr ogram status word . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 sfr definition 9.9. acc: a ccumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 sfr definition 9.10. b: b register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 sfr definition 9.11. pc on: power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 sfr definition 10.1. ie: interrupt enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 sfr definition 10.2. ip: interr upt priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 sfr definition 10.3. eie1: extended interrupt enable 1 . . . . . . . . . . . . . . . . . . . . . . 112 sfr definition 10.4. eip1: extended interrupt priority 1 . . . . . . . . . . . . . . . . . . . . . . 113 sfr definition 10.5. eie2: extended interrupt enable 2 . . . . . . . . . . . . . . . . . . . . . . 114 sfr definition 10.6. eip2: extended interrupt priority 2 . . . . . . . . . . . . . . . . . . . . . . 114 sfr definition 10.7. it01cf: int0/i nt1 configuration . . . . . . . . . . . . . . . . . . . . . . . 116 sfr definition 11.1. mac0cf: mac0 configuration . . . . . . . . . . . . . . . . . . . . . . . . . 122 sfr definition 11.2. mac0sta: mac0 status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 sfr definition 11.3. mac0ah : mac0 a high byte . . . . . . . . . . . . . . . . . . . . . . . . . . 123 sfr definition 11.4. mac0al: mac0 a low byte . . . . . . . . . . . . . . . . . . . . . . . . . . 124 sfr definition 11.5. mac0bh : mac0 b high byte . . . . . . . . . . . . . . . . . . . . . . . . . . 124 rev. 1.0 15 c8051f360/1/2/3/4/5/6/7/8/9 sfr definition 11.6. mac0bl: mac0 b low byte . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 sfr definition 11.7. mac0 acc3: mac0 accumulator byte 3 . . . . . . . . . . . . . . . . . . 125 sfr definition 11.8. mac0 acc2: mac0 accumulator byte 2 . . . . . . . . . . . . . . . . . 125 sfr definition 11.9. mac0 acc1: mac0 accumulator byte 1 . . . . . . . . . . . . . . . . . 125 sfr definition 11.10. mac0 acc0: mac0 accumulator byte 0 . . . . . . . . . . . . . . . . . 126 sfr definition 11.11. mac0 ovr: mac0 accumulator overflow . . . . . . . . . . . . . . . . 126 sfr definition 11.12. ma c0rndh: mac0 rounding register high byte . . . . . . . . . 126 sfr definition 11.13. ma c0rndl: mac0 rounding register low byte . . . . . . . . . 127 sfr definition 12.1. vdm0cn : vdd monitor control . . . . . . . . . . . . . . . . . . . . . . . . 131 sfr definition 12.2. rstsrc: reset source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 sfr definition 13.1. psctl: prog ram store read/write control . . . . . . . . . . . . . . . 142 sfr definition 13.2. flkey: flash lock and key . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 sfr definition 13.3. flscl: flash memory control . . . . . . . . . . . . . . . . . . . . . . . . . 143 sfr definition 14.1. cch0cn : cache control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 sfr definition 14.2. cch0tn : cache tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 sfr definition 14.3. cch0lc: cache lock control . . . . . . . . . . . . . . . . . . . . . . . . . 151 sfr definition 14.4. cch0ma: cac he miss accumulator . . . . . . . . . . . . . . . . . . . . . 152 sfr definition 14.5. flstat: flash stat us . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 sfr definition 15.1. emi0 cn: external memory interface cont rol . . . . . . . . . . . . . . 155 sfr definition 15.2. emi0cf: exter nal memory configuration . . . . . . . . . . . . . . . . . 156 sfr definition 15.3. emi0 tc: external memory timing control . . . . . . . . . . . . . . . . 161 sfr definition 16.1. oscicl: intern al oscillator calibration. . . . . . . . . . . . . . . . . . . 170 sfr definition 16.2. oscicn: inter nal oscillator control . . . . . . . . . . . . . . . . . . . . . 171 sfr definition 16.3. osclcn: inter nal l-f oscillator control . . . . . . . . . . . . . . . . . . 172 sfr definition 16.4. clksel: system clock selection . . . . . . . . . . . . . . . . . . . . . . . 174 sfr definition 16.5. oscxcn: external oscillator c ontrol . . . . . . . . . . . . . . . . . . . . 175 sfr definition 16.6. pll0cn: pll control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 sfr definition 16.7. pll0div: pll pre-divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 sfr definition 16.8. pll0mul: pll cl ock scaler . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 sfr definition 16.9. pll0flt: pll filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 sfr definition 17.1. xbr0: port i/o crossbar regist er 0 . . . . . . . . . . . . . . . . . . . . . 188 sfr definition 17.2. xbr1: port i/o crossbar regist er 1 . . . . . . . . . . . . . . . . . . . . . 189 sfr definition 17.3. p0: port0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 sfr definition 17.4. p0mdin : port0 input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 sfr definition 17.5. p0mdout: port 0 output mode . . . . . . . . . . . . . . . . . . . . . . . . . 191 sfr definition 17.6. p0ski p: port0 skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 sfr definition 17.7. p0mat: port0 ma tch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 sfr definition 17.8. p0mask: port0 mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 sfr definition 17.9. p1: port1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 sfr definition 17.10. p1mdin : port1 input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 sfr definition 17.11. p1mdout: port 1 output mode . . . . . . . . . . . . . . . . . . . . . . . . 194 sfr definition 17.12. p1 skip: port1 skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 sfr definition 17.13. p1mat: port1 ma tch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 sfr definition 17.14. p1mask: port1 mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 sfr definition 17.15. p2: port2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 c8051f360/1/2/3/4/5/6/7/8/9 16 rev. 1.0 sfr definition 17.16. p2mdin : port2 input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 sfr definition 17.17. p2mdout: port 2 output mode . . . . . . . . . . . . . . . . . . . . . . . . 196 sfr definition 17.18. p2 skip: port2 skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 sfr definition 17.19. p2mat: port2 ma tch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 sfr definition 17.20. p2mask: port2 mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 sfr definition 17.21. p3: port3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 sfr definition 17.22. p3mdin : port3 input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 sfr definition 17.23. p3mdout: port 3 output mode . . . . . . . . . . . . . . . . . . . . . . . . 199 sfr definition 17.24. p3 skip: port3 skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 sfr definition 17.25. p4: port4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 sfr definition 17.26. p4mdout: port 4 output mode . . . . . . . . . . . . . . . . . . . . . . . . 200 sfr definition 18.1. smb0cf: smbus clock/configuration . . . . . . . . . . . . . . . . . . . 208 sfr definition 18.2. smb0cn : smbus control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 sfr definition 18.3. smb0dat: smbus data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 sfr definition 19.1. scon0: serial port 0 control . . . . . . . . . . . . . . . . . . . . . . . . . . 225 sfr definition 19.2. sbuf0: serial (uart0) port data buffer . . . . . . . . . . . . . . . . . 226 sfr definition 20.1. spi0cfg: spi0 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 241 sfr definition 20.2. spi0cn: spi0 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 sfr definition 20.3. spi0ck r: spi0 clock rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 sfr definition 20.4. spi0dat: spi0 data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 sfr definition 21.1. tcon: timer cont rol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 sfr definition 21.2. tmod: ti mer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 sfr definition 21.3. ckcon: clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 sfr definition 21.4. tl0: timer 0 low byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 sfr definition 21.5. tl1: timer 1 low byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 sfr definition 21.6. th0: timer 0 hi gh byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 sfr definition 21.7. th1: timer 1 hi gh byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 sfr definition 21.8. tmr2cn: timer 2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 sfr definition 21.9. tmr2rll: ti mer 2 reload register low byte . . . . . . . . . . . . . 259 sfr definition 21.10. tmr2 rlh: timer 2 reload re gister high byte . . . . . . . . . . . 259 sfr definition 21.11. tmr2l: timer 2 low byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 sfr definition 21.12. tmr2h timer 2 high byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 sfr definition 21.13. tmr3cn: timer 3 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 sfr definition 21.14. tmr3 rll: timer 3 reload regi ster low byte . . . . . . . . . . . . 263 sfr definition 21.15. tmr3 rlh: timer 3 reload re gister high byte . . . . . . . . . . . 263 sfr definition 21.16. tmr3l: timer 3 low byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 sfr definition 21.17. tmr3h timer 3 high byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 sfr definition 22.1. pca0cn: pca control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 sfr definition 22.2. pca0md: pca0 mo de . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 sfr definition 22.3. pc a0cpmn: pca0 capture/ compare mode . . . . . . . . . . . . . . 278 sfr definition 22.4. pca0l: pca0 counter/timer low byte . . . . . . . . . . . . . . . . . . 279 sfr definition 22.5. pca0h: pca0 counter/timer high byte . . . . . . . . . . . . . . . . . . 279 sfr definition 22.6. pca0cpln: pc a0 capture module low byte . . . . . . . . . . . . . . 279 sfr definition 22.7. pca0cphn: pc a0 capture module high byte . . . . . . . . . . . . 280 c2 register definition 24.1. c2add: c2 address . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 rev. 1.0 17 c8051f360/1/2/3/4/5/6/7/8/9 c2 register definition 24.2. device id: c2 device id . . . . . . . . . . . . . . . . . . . . . . . . 284 c2 register definition 24.3. revid: c2 revision id . . . . . . . . . . . . . . . . . . . . . . . . . 285 c2 register definition 24.4. fp ctl: c2 flash programming cont rol . . . . . . . . . . . . 285 c2 register definition 24.5. fp dat: c2 flash programming data . . . . . . . . . . . . . . 285 c8051f360/1/2/3/4/5/6/7/8/9 18 rev. 1.0 1. system overview c8051f36x devices are fully integr ated mixed-signal system-on-a-ch ip mcus. highlighted features are listed below. refer to ta b l e 1.1 for specific product feature selection. ? high-speed pipelined 8051-compatible microcontroller core (up to 100 mips) ? in-system, full-speed, non-intrusive debug interface (on-chip) ? true 10-bit 200 ksps 16-channel single-ended/diffe rential ad c with analog multiplexer ? 10-bit current output dac ? 2-cycle 16 by 16 multiply and accumulate engine ? precision programmable 25 mhz internal oscillator ? up to 32 kb of on-chip flash memory?1024 bytes are reserved ? 1024 bytes of on-chip ram ? external data memory interface with 64 kb address space ? smbus/i2c, enhanced uart, and enhanced spi serial interfaces implemented in hardware ? four general-purpose 16-bit timers ? programmable counter/timer array (pca) with six capture/compare modules and watchdog timer func tion ? on-chip power-on reset, v dd monitor, and temperature sensor ? two on-chip voltage comparators ? up to 39 port i/o (5 v tolerant) with on-chip power-on reset, v dd monitor, watchdog timer, and cloc k oscillator, the c8051f36x devices are truly stand-alone system-on-a-chip solutions. the flash memory can be reprogrammed even in-cir - cuit, providing non-volatile data storage, and also a llowin g field upgrades of the 8051 firmware. user soft - ware has complete control of all peripherals, and ma y individually shut down any or all peripherals for power savings. the on-chip silicon labs 2- wire (c2) d evelopment interface allo ws non-intrusive (uses no on-chip resources), full speed, in-circuit debugging using the production mcu installed in the final application. this debug logic supports inspection and modification of memory and registers, setting breakpoints, single stepping, run and halt commands. all analog and digita l peripherals are fully functional while debugging using c2. the two c2 interface pins can be shared with user functions , allowing in-system debugging with - out occupying package pins. each device is specified for 3.0 to 3.6 v (100 mips) op eration or 2.7 to 3.6 v (50 mips) operation over the industrial temperature range (?40 to +85 c). the port i/o and rst pins are tolerant of input signals up to 5 v. the c8051f36x devices are available in 48-pin t qfp packages, and c805 1f36x devices are avail - able in 32-pin lqfp and 28-pin qfn packages (also referred to as mlp or mlf packages). all package types a re lead-free (rohs compliant). see ta b l e 1.1 for ordering part numbers. block diagrams are included in figure 1.1 , figure 1.2 , and figure 1.3 . table 1.1. product selection guide ordering part number mips (peak) flash memory (kb) ram (bytes) 2-cycle 16 by 16 mac calibrated internal 24.5 mhz oscillator internal 80 khz oscillator external memory interface smbus/i 2 c enhanced spi uart timers (16-bit) programmable counter array digital port i/os 10-bit 200ksps adc 10-bit current output dac internal voltage reference temperature sensor analog comparators lead-free (rohs compliant) package c8051f360-gq 100 32 1024 3 3 3 3 3 3 3 4 3 39 3 3 3 3 2 3 tqfp-48 c8051f361-gq 1 100 32 1024 3 3 3 ? 3 3 3 4 3 29 3 3 3 3 2 3 lqfp-32 c8051f362-gm 2 100 32 1024 3 3 3 ? 3 3 3 4 3 25 3 3 3 3 2 3 qfn-28 c8051f363-gq 100 32 1024 3 3 3 3 3 3 3 4 3 39 ? ? ? ? 2 3 tqfp-48 c8051f364-gq 1 100 32 1024 3 3 3 ? 3 3 3 4 3 29 ? ? ? ? 2 3 lqfp-32 C8051F365-GM 2 100 32 1024 3 3 3 ? 3 3 3 4 3 25 ? ? ? ? 2 3 qfn-28 c8051f366-gq 1 50 32 1024 3 3 3 ? 3 3 3 4 3 29 3 3 3 3 2 3 lqfp-32 c8051f367-gm 2 50 32 1024 3 3 3 ? 3 3 3 4 3 25 3 3 3 3 2 3 qfn-28 c8051f368-gq 1 50 16 1024 3 3 3 ? 3 3 3 4 3 29 3 3 3 3 2 3 lqfp-32 c8051f369-gm 2 50 16 1024 3 3 3 ? 3 3 3 4 3 25 3 3 3 3 2 3 qfn-28 notes: 1. pin comp atible with the c8051f310-gq. 2. pin comp atible with the c8051f311-gm. rev. 1.0 19 c8051f360/1/2/3/4/5/6/7/8/9 analog peripherals 2 comparators vref vdd vref 10-bit idac 10-bit 200 ksps adc temp sensor vdd + - cp0 + - cp1 c8051f360 only p4.4 a m u x debug / programming hardware port 0 drivers p0.0 port i/o configuration power-on reset power net p0.1/tx p0.2/rx p0.3/vref p0.4/ida0 p0.5/xtal1 p0.6/xtal2 p0.7/cnvstr port 1 drivers port 2 drivers port 3 drivers port 4 drivers p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 p3.0 p3.1 p3.2 p3.3 p3.4 p3.5 p3.6 p3.7 p4.0 p4.1 p4.2 p4.3 p4.4 p4.5 p4.6/c2d supply monitor external memory interface p0 / p4 p1 sfr bus vdd gnd c2ck/rst reset c2d p2 / p3 / p4 system clock setup external oscillator internal oscillator xtal1 xtal2 low frequency oscillator clock multiplier data control address ain0?ain16 cip-51 8051 controller core 32/16 kb isp flash program memory 256 byte ram 1 kb xram 2-cycle 16 by 16 multiply and accumulate digital peripherals priority crossbar decoder crossbar control uart0 timers 0, 1, 2, 3 pca/wdt smbus spi c8051f360/1/2/3/4/5/6/7/8/9 20 rev. 1.0 figure 1.1. c8051f360/3 block diagram analog peripherals 10-bit idac 10-bit 200 ksps adc temp sensor vdd + - cp0 + - cp1 c8051f361/6/8 only p0.1 a m u x vref vdd vref 2 comparators debug / programming hardware port 0 drivers p0.0/vref port i/o configuration power-on reset p0.1/ida0 p0.2/xtal1 p0.3/xtal2 p0.4/tx p0.5/rx p0.6/cnvstr p0.7 port 1 drivers port 2 drivers port 3 drivers p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 p3.0/c2d p3.1 p3.2 p3.3 p3.4 supply monitor sfr bus vdd gnd c2ck/rst reset ain0?ain20 system clock setup external oscillator internal oscillator xtal1 xtal2 low frequency oscillator clock multiplier cip-51 8051 controller core 32/16 kb isp flash program memory 256 byte ram 1 kb xram 2-cycle 16 by 16 multiply and accumulate c2d digital peripherals priority crossbar decoder crossbar control uart0 timers 0, 1, 2, 3 pca/wdt smbus spi analog peripherals 2 comparators 10-bit idac 10-bit 200 ksps adc temp sensor vdd + - cp0 + - cp1 c8051f362/7/9 only p0.1 a m u x vref vdd vref debug / programming hardware port 0 drivers p0.0/vref port i/o configuration power-on reset p0.1/ida0 p0.2/xtal1 p0.3/xtal2 p0.4/tx p0.5/rx p0.6/cnvstr p0.7 port 1 drivers port 2 drivers port 3 drivers p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 p3.0/c2d supply monitor sfr bus vdd gnd c2ck/rst reset c2d system clock setup external oscillator internal oscillator xtal1 xtal2 low frequency oscillator clock multiplier cip-51 8051 controller core 32/16 kb isp flash program memory 256 byte ram 1 kb xram 2-cycle 16 by 16 multiply and accumulate ain0?ain20 digital peripherals priority crossbar decoder crossbar control uart0 timers 0, 1, 2, 3 pca/wdt smbus spi rev. 1.0 21 c8051f360/1/2/3/4/5/6/7/8/9 figure 1.2. c8051f361/4/6/8 block diagram figure 1.3. c8051f362/5/7/9 block diagram c8051f360/1/2/3/4/5/6/7/8/9 22 rev. 1.0 1.1. cip-51? microcontroller core 1.1.1. fully 8051 compatible the c8051f36x family utilizes silicon labs' proprietary cip-51 microc ontroller core. the cip-51 is fully compatible with the mcs-51? instruction set; standard 803x/805x assemblers and compilers can be used to develop software. the cip-51 core offers all th e peripherals included with a standard 8052, including four 16-bit counter/timers, a full- duplex uart with extended baud rate configuration, an enhanced spi port, 1024 bytes of internal ram, 128 byte special function register (s f r) address space, and up to 39 i/o pins. 1.1.2. improved throughput the cip-51 employs a pipelined architecture that grea tly increases its instruction throughput over the stan - dard 8051 architecture. in a standar d 8051, all inst ructions except for mul and div take 12 or 24 system clock cycles to execute with a ma ximum system clock of 12-to-24 mhz. by contrast, the cip-51 core exe - cutes 70% of its instructions in one or two system clock cy cles, with only four inst ructions taking more than four system clock cycles. the cip-51 has a total of 109 instructions. the table be low shows the total number of instructions that require each execution time. clocks to execute 1 2 2/3 3 3/4 4 4/5 5 8 number of instructions 26 50 5 14 7 3 1 2 1 with the cip-51's maximu m s ystem clock at 100 mhz, it has a peak throughput of 100 mips. figure 1.4 shows a comparison of peak throughputs for variou s 8 -bit microcontroller cores with their maximum sys - tem clocks. 5 10 15 20 aduc812 8051 (16 mhz clk) philips 80c51 (33 mhz clk) microchip pic17c75x (33 mhz clk) silicon labs cip-51 (25 mhz clk) mips 25 figure 1.4. comparison of peak mcu execution speeds rev. 1.0 23 c8051f360/1/2/3/4/5/6/7/8/9 1.1.3. additional features the c8051f36x soc family includes several key enhancements to the cip-51 core and peripherals to improve performance and ease of use in end applications. the extended interrupt handler provi des 16 inte rrupt sources into the cip-51 (as opposed to 7 for the stan - dard 8051), allowing numerous analog and digital peripherals to interrupt the controller. an interrupt driven sys tem requires less interv ention by the mcu, giving it more effe ctive throughput. the extra interrupt sources are very useful when build ing multi-tasking, real-time systems. eight reset sources are available: power-on reset circuitry (por), an on-chip v dd monitor (forces reset when power supply voltage drops below v rst as given in table 12.1 on page 134 ), a watchdog timer, a missing clock detector, a voltage level detection from comparator0, a forced software reset, an external r eset pin, and an illegal flash access protection circui t. each reset source except for the por, reset input pin, or flash error may be disabled by the user in software. the wdt may be permanently enabled in soft - ware after a power-on rese t during mcu initialization. the internal oscillator fa ctory c alibrated to 24.5 mhz 2%. this internal oscillato r period may be user pro - grammed in ~0.5% increments. an additional lo w-frequency oscillator is also available which facilitates low-power operation. an ex ternal oscillator drive circuit is includ ed, allowing an exter nal crystal, ceramic resonator, capacitor, rc, or cmos clock source to generate the system clock. if desired, the system clock source may be switched on-t he-fly between both internal and external oscillator ci rcuits. an external oscil - lator can also be extremely useful in low power applic ations, allowing the mcu to run from a slow (power saving) source, while periodically switching to the fast (up to 25 mhz) internal oscilla tor as needed. addi - tionally, an on-chip pll is provided to achieve hi gh er system clock speeds for increased throughput. pca wdt missing clock detector (one- shot) (software reset) system reset reset funnel px.x px.x en swrsf system clock cip-51 microcontroller core extended interrupt handler clock select en wdt enable mcd enable errant flash operation /rst (wired-or) power on reset '0' + - comparator 0 c0rsef vdd + - supply monitor enable xtal1 xtal2 external oscillator drive low frequency oscillator internal oscillator pll circuitry figure 1.5. on-chi p clock and reset c8051f360/1/2/3/4/5/6/7/8/9 24 rev. 1.0 1.2. on-chip memory the cip-51 has a standard 8051 program and data addr ess configuration. it in cludes 256 bytes of data ram, with the upper 128 bytes dual-mapped. indirect addressing accesses the upper 128 bytes of general purpose ram, and direct addressing accesses the 128 byte sfr addre ss space. the lower 128 bytes of ram are accessible via direct and indirect addressing. the first 32 bytes are addressable as four banks of general purpose registers, and the next 16 byte s can be byte addressable or bit addressable. program memory consists of 32/16 kb of flash. this memory may be reprogrammed in-system in 1024 by te sectors, and requires no special off-chip programming voltage. see figure 1.6 for the mcu system memory map. flash (in-system programmable in 1024 byte sectors) program memory 0x0000 (direct and indirect addressing) 0x00 0x7f upper 128 ram (indirect addressing only) 0x80 0xff special function register's (direct addressing only) reserved 0x7c00 0x7bff data memory general purpose registers 0x1f 0x20 0x2f bit addressable lower 128 ram (direct and indirect addressing) 0x30 c8051f360/1/2/3/4/5/6/7 flash (in-system programmable in 1024 byte sectors) 0x0000 0x4000 0x3fff c8051f368/9 external data address space internal data address space xram - 1024 bytes (accessable using movx instruction) 0x0000 0x03ff same 1024 bytes as from 0x0000 to 0x03ff, wrapped on 1024-byte boundaries 0x0400 0xffff reserved figure 1.6. on-board memory map 1.3. on-chip debug circuitry the c8051f36x devices inclu de on-chip silicon labs 2-wire (c2) de bug circuitry that provides non-intru - sive, full speed, in-circuit debugging of the production part inst alled in the end application. silicon labs' debugging syst em support s inspection and modificati on of memory and registers, break - points, and single stepping. no additional target ram, pr ogram memory, timers, or communications chan - rev. 1.0 25 c8051f360/1/2/3/4/5/6/7/8/9 nels are required. all the digital and analog periphera ls are functional and work correctly while debugging. all the peripherals (except for the adc and smbus) are stalled when the mcu is halted, during single stepping, or at a breakpoint in order to keep them synchronized. the c8051f360dk development kit provides all the har dware and software necessary to develop applica - tion code and perform in-circuit debugging with the c8051f36x mcus. the kit includes software with a developer's studio and debugger, an integrated 8051 assembler, and a debug adapter. it also has a target application board with the associated mcu installed and prototyping area, plus the required cables, and wall-mount power supply. the development kit requires a pc running windows98se or later. the silicon labs ide interface is a vastl y superior developing and debu gging configuratio n, compared to standard mcu emulators that use on-board "ice chips" and require the mcu in the application board to be socketed. silicon labs' debug para digm increases ease of use and preserves the performance of the precision analog peripherals. target pcb debug adapter vdd gnd c2 (x2), vdd, gnd windows 2000 or later silicon labs integrated development environment c8051f360 figure 1.7. development/in -system debug diagram 1.4. programmable digital i/o and crossbar c8051f36x devices include up to 39 i/o pins (fou r byte-wide ports and one 7-bit-wide port). the c8051f36x ports behave like typical 8051 ports with a few enhancements. each port pin may be config - ured as an analog input or a digital i/o pin. pins sele cted as dig ital i/os may additionally be configured for push-pull or open-drain output. the ?weak pullups? that are fixed on typical 8051 devices may be globally disabled, providing powe r savings capabilities. c8051f360/1/2/3/4/5/6/7/8/9 26 rev. 1.0 the digital crossbar allows mapping of internal digi tal system resources to port i/o pins. (see figure 1.8.) on-chip counter/timers, serial buses, hw interrupts, com parator output, and other digital signals in the controller can be configured to appear on the port i/o pins specified in the crossbar control registers. this allows the user to select the exact mix of general purpose port i/o and digital resources needed for the particular application. xbr0, xbr1, pnskip registers digital crossbar priority decoder 2 p0 i/o cells p0.0 p0.7 8 p0mask, p0match p1mask, p1match, p2mask, p2match registers uart (internal digital signals) highest priority lowest priority sysclk 2 smbus t0, t1 2 7 pca 4 cp0 cp1 outputs spi 4 (port latches) p0 (p0.0-p0.7) (p1.0-p1.7) 8 8 p1 p2 (p2.0-p2.7) 8 pnmdout, pnmdin registers 3.5?3.7 available on c8051f360/3 p3 (p3.0-p3.7) 8 p1 i/o cells p1.0 p1.7 8 p2 i/o cell 8 p2.0 p2.7 p3 i/o cells p3.0 p3.7 8 3.1?3.4 available on c8051f360/1/3/4/6/8 figure 1.8. digital crossbar diagram (port 0 to port 3) 1.5. serial ports the c8051f36x family includes an smbus/i 2 c interface, a full-duplex uart with enhanced baud rate configuration, and an enhanced spi interface. each of the serial buses is fully implemented in hardware and makes extensive use of the cip-51's interrup ts, thus requiring very little cpu intervention. 1.6. programmable counter array an on-chip programmable counter/timer array (pca) is included in addition to the four 16-bit general pur - pose counter/timers. the pca consists of a dedicated 16-bit counter/ timer time base with three program - mable capture/compare modules. the pca clock is de rived from one of six so urces: the system clock divided by 12, the system clock divided by 4, timer 0 overflows, an external cl ock input (eci), the system clock, or the external osc illator clock source divided by 8. the extern al clock source selection is useful for rev. 1.0 27 c8051f360/1/2/3/4/5/6/7/8/9 real-time clock functi onality, where the pca is clocked by an exte rnal source while the internal oscillator drives the system clock. each capture/compare module can be configured to operate in one of six modes: edge-triggered capture, software timer, high speed output, 8- or 16-bit pulse width modulator, or frequency output. additionally, capture/compare module 5 offers watchdog timer (wdt) capabilit ies. following a system reset, module 5 is configured and enabled in wdt mode. the pca capture/compare module i/o and external clock input may be routed to port i/o via the digital crossbar. capture/compare module 1 capture/compare module 0 capture/compare module 2 capture/compare module 3 cex1 eci crossbar cex2 cex3 cex0 port i/o 16-bit counter/timer pca clock mux sysclk/12 sysclk/4 timer 0 overflow eci sysclk external clock/8 capture/compare module 4 cex4 capture/compare module 5 cex5 figure 1.10. pca block diagram 1.7. 10-bit analog to digit al converter the c8051f360/1/2/6/7/8/9 devices include an on-chip 10-bit sar adc with up to 21 channels for the dif - ferential input multiplexer. with a maximum throughput of 200 ksps, the adc offers true 10-bit linearity with a n inl and dnl of 1 lsb. the adc system includes a configurab le analog multiplexe r t hat selects both positive and negative adc inputs. ports1-3 are available as an adc inputs; additionally, the on-chip tem - perature sensor output and the power supply voltage (v dd ) are available as adc inputs. user firmware may shut down the adc to save power. conversions can be started in six ways: a software comma nd, a n overflow of timer 0, 1, 2, or 3, or an external convert start signal (cnvstr). this flexibility a llows the start of conversion to be triggered by soft - ware events, a periodic signal (timer overflows), or e xternal hw signals. conversion completions are indi - c8051f360/1/2/3/4/5/6/7/8/9 28 rev. 1.0 cated by a status bit and an interrupt (if enabled). th e resulting 10-bit data word is latched into the adc data sfrs upon completion of a conversion. window compare registers for the adc data can be conf igured to interrupt the co ntroller when adc data is either within or outside of a specified range. the adc can monitor a key voltage continuously in back - ground mode, but not interrupt the controller unless the converted data is within/outside the specified range. adc0cf ad0ljst ad0sc0 ad0sc1 ad0sc2 ad0sc3 ad0sc4 10-bit sar adc ref sysclk adc0h 32 adc0cn ad0cm0 ad0cm1 ad0cm2 ad0wint ad0busy ad0int ad0tm ad0en timer 0 overflow timer 2 overflow timer 1 overflow start conversion 000 ad0busy (w) vdd adc0lth 23-to-1 amux ad0wint temp sensor 23-to-1 amux vdd p1.0 p1.7 001 010 011 100 cnvstr input window compare logic p2.0 p2.7 gnd p1.0 p1.7 p2.0 p2.7 p3.0 p3.4 101 timer 3 overflow adc0ltl adc0gth adc0gtl adc0l amx0p amx0p4 amx0p3 amx0p2 amx0p1 amx0p0 amx0n amx0n4 amx0n3 amx0n2 amx0n1 amx0n0 p3.0 p3.4 p3.1-3.4 available on c8051f360/1/6/8 (+) (-) vref p3.1-3.4 available on c8051f360/1/6/8 p1.0-1.3 available on c8051f361/2/6/7/8/9 p1.0-1.3 available on c8051f361/2/6/7/8/9 figure 1.11. 10-bit adc block diagram 1.8. comparators c8051f36x devices include two on-chip voltage comparat ors that are enabled/disabled and configured via user software. port i/o pins may be configured as comparator inputs via a selection mux. two comparator outputs may be routed to a port pin if desired: a latched output and/or an unlatched (asynchronous) output. comparator response time is programmable, allowi ng the user to select between high-speed and low- power modes. positive and negative hysteresis are also configurable. comparator interrupts may be generated on rising, falling, or both edges. when in idle mode, these inter - rupts may be used as a ?wake-up? source. comparator0 may also be configured as a reset source. figure 1.12 shows the comparator0 block diagram, and figure 1.13 shows the comparator1 block dia - gram. note: t he first port i/o pins shown in figure 1.12 and figure 1.13 are for the 48-pin (c8051f360/3) devices. the second set of port i/o pins are for th e 32-pin and 28-pin (c8051f361/2/4/5/6/7/8/9) devices. please refer to the cptnmx registers ( sfr definition 8.2 and sfr definition 8.5 ) for more information. vdd cpt0cn reset decision tree + - crossbar q q set clr d q q set clr d (synchronizer) gnd cp0 + cp0 - cp0en cp0out cp0rif cp0fif cp0hyp1 cp0hyp0 cp0hyn1 cp0hyn0 cpt0mx cmx0n3 cmx0n2 cmx0n1 cmx0n0 cmx0p1 cmx0p0 cpt0md cp0rie cp0fie cp0md1 cp0md0 cp0 cp0a cp0 interrupt 0 1 0 1 cp0rif cp0fif 0 1 cp0en 0 1 ea p1.5 / p1.1 p2.4 / p1.5 p3.2 / p2.1 p3.6 / p2.5 p1.4 / p1.0 p2.3 / p1.4 p3.1 / p2.0 p3.5 / p2.4 rev. 1.0 29 c8051f360/1/2/3/4/5/6/7/8/9 figure 1.12. comparator0 block diagram vdd cpt1cn + - crossbar q q set clr d q q set clr d (synchronizer) gnd cp1 + cp1 - cpt1mx cp1 cp1a cp1 interrupt 0 1 0 1 cp1rif cp1fif 0 1 cp1en 0 1 ea p2.1 / p1.3 p2.6 / p1.7 p3.4 / p2.3 p4.0 / p2.7 p2.0 / p1.2 p2.5 / p1.6 p3.3 / p2.2 p3.7 / p2.6 cmx1n0 cmx1p1 cmx1p0 cmx1n1 cp1en cp1out cp1rif cp1fif cp1hyp1 cp1hyp0 cp1hyn1 cp1hyn0 cpt1md cp1rie cp1fie cp1md1 cp1md0 c8051f360/1/2/3/4/5/6/7/8/9 30 rev. 1.0 figure 1.13. comparator1 block diagram 1.9. 10-bit current output dac the c8051f360/1/2/6/7/8/9 devices includes a 10-bit current-mod e digital-to-analog converter (ida0). the maximum current output of the ida0 can be ad justed for three different current settings; 0.5 ma, 1 ma, and 2 ma. ida0 features a flexible o utput update mechanism which allows for seamless full-scale changes and supports jitter-free updates for wavefo rm generation. three update modes are provided, allowing ida0 output updates on a write to ida0h, on a timer overflow, or on an external pin edge. ida0 10 ida0 ida0cn ida0en ida0cm2 ida0cm1 ida0cm0 ida0omd1 ida0omd0 ida0h ida0l latch 8 2 ida0h timer 0 timer 1 timer 2 timer 3 cnvstr rev. 1.0 31 c8051f360/1/2/3/4/5/6/7/8/9 figure 1.14. ida0 functional block diagram c8051f360/1/2/3/4/5/6/7/8/9 32 rev. 1.0 2. absolute maximum ratings table 2.1. absolute maximum ratings note: stresses above those listed under ?absolute maximum ra tings? may cause permanent damage to the device. this is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation list ings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. parameter conditions min typ max units ambient temperature under bias ?55 ? 125 c storage temperature ?65 ? 150 c voltage on any port i/o pin or rst with respect to gnd ?0.3 ? 5.8 v voltage on v dd with respect to gnd ?0.3 ? 4.2 v maximum total current through v dd or gnd ? ? 500 ma maximum output current sunk by rst or any port pin ??100ma rev. 1.0 33 c8051f360/1/2/3/4/5/6/7/8/9 3. global electrical characteristics table 3.1. global electrical characteristics ?40 to +85 c, 25 mhz system clock unless otherwise specified. parameter conditions min typ max units digital supply voltage sysclk = 0 to 50 mhz sysclk > 50 mhz 2.7 3.0 3.0 3.3 3.6 3.6 v digital supply ram data retention voltage ?1.5? v sysclk (system clock) 1,2 c8051f360/1/2/3/4/5 c8051f366/7/8/9 0 0 ? ? 100 50 mhz mhz specified operating temperature range ?40 ? +85 c digital supply current?cpu active (normal mode, fetching instructions from flash) i dd 2 v dd = 3.6 v, f = 100 mhz ? 68 75 ma v dd = 3.6 v, f = 25 mhz ? 21 25 ma v dd = 3.0 v, f = 100 mhz ? 54 60 ma v dd = 3.0 v, f = 25 mhz ? 16 18 ma v dd = 3.0 v, f = 1 mhz ? 0.48 ? ma v dd = 3.0 v, f = 80 khz ? 36 ? a i dd supply sensitivity 3 f = 25 mhz ? 56 ? %/v f = 1 mhz ? 57 ? %/v i dd frequency sensitivity 3,4 v dd = 3.0 v, f <= 20 mhz, t = 25 c ? 0.45 ? ma/mhz v dd = 3.0 v, f > 20 mhz, t = 25 c ? 0.38 ? ma/mhz v dd = 3.6 v, f <= 20 mhz, t = 25 c ? 0.61 ? ma/mhz v dd = 3.6 v, f > 20 mhz, t = 25 c ? 0.51 ? ma/mhz c8051f360/1/2/3/4/5/6/7/8/9 34 rev. 1.0 other electrical characteristics tables are found in the data sheet section corresponding to the associated peripherals. for more information on electrical characte ristics for a specific perip heral, refer to the page indicated in ta b l e 3.2 . digital supply current?cpu in a ctive (idle mode, not fetching instructions from flash) i dd 2 v dd = 3.6 v, f = 100 mhz ? 36 40 ma v dd = 3.6 v, f = 25 mhz ? 9 12 ma v dd = 3.0 v, f = 100 mhz ? 30 35 ma v dd = 3.0 v, f = 25 mhz ? 7 9 ma v dd = 3.0 v, f = 1 mhz ? 0.24 ? ma v dd = 3.0 v, f = 80 khz ? 19 ? a i dd supply sensitivity 3 f = 25 mhz ? 44 ? %/v f = 1 mhz ? 43.7 ? %/v i dd frequency sensitivity 3,5 v dd = 3.0 v, f <= 1 mhz, t = 25 c ? 0.24 ? ma/mhz v dd = 3.0 v, f > 1 mhz, t = 25 c ? 0.25 ? ma/mhz v dd = 3.6 v, f <= 1 mhz, t = 25 c ? 0.31 ? ma/mhz v dd = 3.6 v, f > 1 mhz, t = 25 c ? 0.32 ? ma/mhz digital supply current (stop mode, shutdown) oscillator not running, v dd monitor disabled ?< 0.1? a notes: 1. sysclk must be at least 32 khz to enable debugging. 2. sysclk is the internal device clo ck. for operational speeds in excess of 30 mhz, sysclk must be derived from the phase-locked loop (pll). 3. base d on device characterization data; not production tested. 4. idd ca n be estimated for frequencies < 20 mhz by simply multiplying the frequency of interest by the frequency sen sitivity number for that range. w hen using these numbers to estimate i dd for >20 mhz, the esti mate should be the current at 25 mhz minus the difference in current indicated by the frequency sensitivity number. for e xample: v dd = 3.0 v; f = 20 mhz, i dd = 15.9 ma - (25 mhz - 20 mhz) * 0.38 ma/mhz = 14 ma. 5. idle idd can be estimated for frequencies < 1 mhz by simply multiplying the frequency of interest by the frequ ency sensitivity number for that range. when using these numbers to estimate idle i dd for >1 mhz, the estimate shou ld be the current at 25 mhz minus the difference in current ind icated by the frequency sensitivity number. for example: v dd = 3.0 v; f = 5 mhz, idle i dd = 7.2 ma - (25 mhz - 5 mhz) * 0.25 ma/mhz = 2.2 ma. table 3.1. global electrical characteristics (continued) ?40 to +85 c, 25 mhz system clock unless otherwise specified. parameter conditions min typ max units table 3.2. index to electrical ch aracteristics t ables peripheral electrical characteristics page no. adc0 electrical characteristics 62 idac electrical characteristics 66 voltage reference electrical characteristics 69 comparator electrical characteristics 79 reset electrical characteristics 134 flash electrical characteristics 144 internal high frequency oscillato r e lectrical characteristics 171 internal low frequency oscillato r elec trical characteristics 172 pll frequency characteristics 182 port i/o dc electrical characteristics 201 rev. 1.0 35 c8051f360/1/2/3/4/5/6/7/8/9 c8051f360/1/2/3/4/5/6/7/8/9 36 rev. 1.0 4. pinout and package definitions table 4.1. pin definitions for the c8051f36x name pin ?f360/3 (48-pin) pin ?f36 1/4/6/8 (32-pin) pin ?f362/5/7/9 (28-pin) type description v dd 19, 31, 43 4 4 power supply voltage. gnd 18, 30, 42 3 3 ground. agnd 6 ? ? analog ground. av+ 7 ? ? analog supply voltage. must be tied to +2.7 to +3.6 v. rst / c2ck 8 5 5 d i/o d i/o device reset. open-drain output of internal por or v dd monitor. an external source can initiate a system reset by driving this pin low for at least 10 s. clock signal for the c2 debug interface. p4.6/ c2d 9 ? ? d i/o or a in d i/o port 4.6. see section 17 fo r a complete description. bi-directional data signal for the c2 debug interface. p3.0/ c2d ? 6 6 d i/o or a in d i/o port 3.0. see section 17 fo r a complete description. bi-directional data signal for the c2 debug interface. p0.0 5 2 2 d i/o or a in port 0.0. see section 17 fo r a complete description. p0.1 4 1 1 d i/o or a in port 0.1. see section 17 fo r a complete description. p0.2 3 32 28 d i/o or a in port 0.2. see section 17 fo r a complete description. p0.3 2 31 27 d i/o or a in port 0.3. see section 17 fo r a complete description. p0.4 1 30 26 d i/o or a in port 0.4. see section 17 fo r a complete description. p0.5 48 29 25 d i/o or a in port 0.5. see section 17 fo r a complete description. p0.6 47 28 24 d i/o or a in port 0.6. see section 17 fo r a complete description. p0.7 46 27 23 d i/o or a in port 0.7. see section 17 fo r a complete description. rev. 1.0 37 c8051f360/1/2/3/4/5/6/7/8/9 p1.0 45 26 22 d i/o or a in port 1.0. see section 17 fo r a complete description. p1.1 44 25 21 d i/o or a in port 1.1. see section 17 fo r a complete description. p1.2 41 24 20 d i/o or a in port 1.2. see section 17 fo r a complete description. p1.3 40 23 19 d i/o or a in port 1.3. see section 17 fo r a complete description. p1.4 39 22 18 d i/o or a in port 1.4. see section 17 fo r a complete description. p1.5 38 21 17 d i/o or a in port 1.5. see section 17 fo r a complete description. p1.6 37 20 16 d i/o or a in port 1.6. see section 17 fo r a complete description. p1.7 36 19 15 d i/o or a in port 1.7. see section 17 fo r a complete description. p2.0 35 18 14 d i/o or a in port 2.0. see section 17 fo r a complete description. p2.1 34 17 13 d i/o or a in port 2.1. see section 17 fo r a complete description. p2.2 33 16 12 d i/o or a in port 2.2. see section 17 fo r a complete description. p2.3 32 15 11 d i/o or a in port 2.3. see section 17 fo r a complete description. p2.4 29 14 10 d i/o or a in port 2.4. see section 17 fo r a complete description. p2.5 28 13 9 d i/o or a in port 2.5. see section 17 fo r a complete description. p2.6 27 12 8 d i/o or a in port 2.6. see section 17 fo r a complete description. p2.7 26 11 7 d i/o or a in port 2.7. see section 17 fo r a complete description. p3.0 25 ? ? d i/o or a in port 3.0. see section 17 fo r a complete description. table 4.1. pin definitions for the c8051f36x (continued) name pin ?f360/3 (48-pin) pin ?f361/4/6/8 (32-pin) pin ?f362/5/7/9 (28-pin) type description c8051f360/1/2/3/4/5/6/7/8/9 38 rev. 1.0 p3.1 24 7 ? d i/o or a in port 3.1. see section 17 fo r a complete description. p3.2 23 8 ? d i/o or a in port 3.2. see section 17 fo r a complete description. p3.3 22 9 ? d i/o or a in port 3.3. see section 17 fo r a complete description. p3.4 21 10 ? d i/o or a in port 3.4. see section 17 fo r a complete description. p3.5 20 ? ? d i/o or a in port 3.5. see section 17 fo r a complete description. p3.6 17 ? ? d i/o or a in port 3.6. see section 17 fo r a complete description. p3.7 16 ? ? d i/o or a in port 3.7. see section 17 fo r a complete description. p4.0 15 ? ? d i/o or a in port 4.0. see section 17 fo r a complete description. p4.1 14 ? ? d i/o port 4.1. see section 17 fo r a complete description. p4.2 13 ? ? d i/o port 4.2. see section 17 fo r a complete description. p4.3 12 ? ? d i/o port 4.3. see section 17 fo r a complete description. p4.4 11 ? ? d i/o port 4.4. see section 17 fo r a complete description. p4.5 10 ? ? d i/o port 4.5. see section 17 fo r a complete description. table 4.1. pin definitions for the c8051f36x (continued) name pin ?f360/3 (48-pin) pin ?f361/4/6/8 (32-pin) pin ?f362/5/7/9 (28-pin) type description 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 45 44 43 42 41 40 39 38 37 p4.3 p1.7 p1.5 p1.4 p1.3 p1.1 vdd p2.1 p2.0 p3.1 p3.0 p2.7 p2.5 p2.4 p1.6 p4.0 p3.6 p3.7 p0.5 p3.4 p2.6 p0.6 p0.1 p0.0 agnd av+ p4.5 p4.4 p0.2 vdd gnd gnd p1.2 p0.4 p1.0 p0.7 p0.3 vdd 13 14 15 16 17 18 19 20 21 22 23 24 p3.3 p3.2 p2.3 p2.2 c8051f360/3 /rst/c2ck p4.6/c2d p4.2 p4.1 gnd p3.5 rev. 1.0 39 c8051f360/1/2/3/4/5/6/7/8/9 figure 4.1. tqfp-48 pi nout diagram (top view) table 4.2. tqfp-48 package dimensions dimension min nom max dimension min nom max notes: 1. all dimen sions shown are in millimeters (mm) unless otherwise noted. 2. dimensi oning and tolerancing per ansi y14.5m-1994. 3. thi s drawing conforms to jedec outline ms-026, variation abc. 4. recommend ed card reflow profile is per the jedec/ipc j-std-020c specification for small body components. c8051f360/1/2/3/4/5/6/7/8/9 40 rev. 1.0 figure 4.2. tqfp-48 package diagram a ? ? 1.20 e 9.00 bsc. a1 0.05 ? 0.15 e1 7.00 bsc. a2 0.95 1.00 1.05 l 0.45 0.60 0.75 b 0.17 0.22 0.27 aaa 0.20 c 0.09 ? 0.20 bbb 0.20 d 9.00 bsc. ccc 0.08 d1 7.00 bsc. ddd 0.08 e 0.50 bsc. 0 3.5 7 1 p3.2 p1.2 p1.7 p1.4 p1.3 p1.5 vdd /rst/c2ck gnd p0.1 p0.0 p2.0 p2.1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 p1.6 c8051f361/4/6/8 p3.0/c2d p3.1 p3.3 p3.4 p2.7 p2.6 p2.5 p2.4 p2.3 p2.2 p1.1 p1.0 p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 rev. 1.0 41 c8051f360/1/2/3/4/5/6/7/8/9 figure 4.3. lqfp-32 pi nout diagram (top view) table 4.3. lqfp-32 package dimensions dimension min nom max dimension min nom max a ? ? 1.60 e 9.00 bsc. a1 0.05 ? 0.15 e1 7.00 bsc. a2 1.35 1.40 1.45 l 0.45 0.60 0.75 b 0.30 0.37 0.45 aaa 0.20 c 0.09 ? 0.20 bbb 0.20 d 9.00 bsc. ccc 0.10 d1 7.00 bsc. ddd 0.20 e 0.80 bsc. 0 3.5 7 notes: 1. al l dimensions shown are in mil limeters (mm) unless otherwise noted. 2. di mensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to je dec outline ms-026, variation bba. 4. re commended card reflow profile is per the jede c/ipc j-std-020b specification for small body components. c8051f360/1/2/3/4/5/6/7/8/9 42 rev. 1.0 figure 4.4. lqfp-32 package diagram 4 5 6 7 2 1 3 11 12 13 14 9 8 10 18 17 16 15 20 21 19 25 26 27 28 23 22 24 c8051f362/5/7/9 p0.1 p0.0 gnd vdd /rst/c2ck p3.0/c2d p2.7 p2.6 p2.5 p2.4 p2.3 p2.2 p2.1 p2.0 p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 gnd rev. 1.0 43 c8051f360/1/2/3/4/5/6/7/8/9 figure 4.5. qfn-28 pino ut diagram (top view) table 4.4. qfn-28 package dimensions dimension min nom max dimension min nom max a 0.80 0.90 1.00 e2 2.90 3.15 3.35 a1 0.03 0.07 0.11 l 0.45 0.55 0.65 a3 0.25 ref aaa 0.15 b 0.18 0.25 0.30 bbb 0.10 d 5.00 bsc. ddd 0.05 d2 2.90 3.15 3.35 eee 0.08 e 0.50 bsc. z 0.435 e 5.00 bsc. y 0.18 notes: 1. al l dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimensio ning and tolerancing per ansi y14.5m-1994. 3. thi s drawing conforms to jedec outline mo-243, variation vhhd except for custom features d2, e2, l, z, and y which are toleranced per supplier designation. 4. recommend ed card reflow profile is per the jede c/ipc j-std-020c specification for small body components. c8051f360/1/2/3/4/5/6/7/8/9 44 rev. 1.0 figure 4.6. qfn-28 package drawing rev. 1.0 45 c8051f360/1/2/3/4/5/6/7/8/9 figure 4.7. typical qf n-28 landing diagram c8051f360/1/2/3/4/5/6/7/8/9 46 rev. 1.0 figure 4.8. qfn-28 solder paste recommendation rev. 1.0 47 c8051f360/1/2/3/4/5/6/7/8/9 5. 10-bit adc (adc0, c8 051f360/1/2/6/7/8/9) the adc0 subsystem for the c8051f360/1/2/6/7/8/9 cons ists of two analog multiplexers (referred to col - lectively as amux0) with 23 total input selections, and a 200 ksps, 10-bit successive-approximation-regis - ter adc with integrated track-and-hold and programmable window detector. the amux0, d ata conversion modes, and window detector are all configurable under software control via the sp ecial function registers shown in figure 5.1 . adc0 operates in both single-ended and differential modes, and may be configured to measure p1.0-p3.4 (where available), the temperature sensor output, or v dd with respect to p1.0- p3.4, vref, or gnd. the adc0 subsystem is enable d only when the ad0en bit in the adc0 control reg - ister (adc0cn) is set to logic ?1?. the adc0 subsystem is in low power s hutdown when this bit is logic ?0?. adc0cf ad0ljst ad0sc0 ad0sc1 ad0sc2 ad0sc3 ad0sc4 10-bit sar adc ref sysclk adc0h 32 adc0cn ad0cm0 ad0cm1 ad0cm2 ad0wint ad0busy ad0int ad0tm ad0en timer 0 overflow timer 2 overflow timer 1 overflow start conversion 000 ad0busy (w) vdd adc0lth 23-to-1 amux ad0wint temp sensor 23-to-1 amux vdd p1.0 p1.7 001 010 011 100 cnvstr input window compare logic p2.0 p2.7 gnd p1.0 p1.7 p2.0 p2.7 p3.0 p3.4 101 timer 3 overflow adc0ltl adc0gth adc0gtl adc0l amx0p amx0p4 amx0p3 amx0p2 amx0p1 amx0p0 amx0n amx0n4 amx0n3 amx0n2 amx0n1 amx0n0 p3.0 p3.4 p3.1-3.4 available on c8051f360/1/6/8 (+) (-) vref p3.1-3.4 available on c8051f360/1/6/8 p1.0-1.3 available on c8051f361/2/6/7/8/9 p1.0-1.3 available on c8051f361/2/6/7/8/9 figure 5.1. adc0 functional block diagram c8051f360/1/2/3/4/5/6/7/8/9 48 rev. 1.0 5.1. analog multiplexer amux0 selects the positive and negative inputs to th e adc. any of the following may be selected as the positive input: the amux0 port i/o inputs, the on-c hip temperature sensor, or the positive power supply (v dd ). any of the following may be selected as the negative input: the amux0 port i/o inputs, vref, or gnd. when gnd is selected as the ne gative input, adc0 operates in single-en ded mode; all other times, adc0 operates in differential mode. the adc0 input channels are selected in the amx0p and amx0n registers as described in sfr definition 5.1 and sfr definition 5.2 . the conversion code format differs between single -en ded and differential modes. the registers adc0h and adc0l contain the high and low bytes of the output conversion code from the adc at the completion of each conversion. data can be right-justified or left -justified, depending on the setting of the ad0ljst bit (adc0cn.0). when in single-ended mode, conversion codes are represented as 10-bit unsigned integers. inputs are measured from ?0? to vref * 1023/1024. ex ample codes are shown below for both right-justified and left-justified data. unused bits in the adc0h and adc0l registers are set to ?0?. when in differential mode, conversion codes are represented as 10-bit signed 2?s complement numbers. inp uts are measured from -vref to vref * 511/512. example codes are shown below for both right-justi - fied and left-justified data. for ri ght-j ustified data, the unused msbs of adc0h are a sign-extension of the data word. for left-justified data, the unused lsbs in the adc0l register are set to ?0?. important note about adc0 input configuration: por t pins selected as adc0 inputs should be config - ured as analog inputs, and should be skipped by the dig ital crossbar. to configure a port pin for analog input, set to ?0? the corresponding bit in register pnmd in (for n = 0,1,2,3). to fo rce the crossbar to skip a port pin, set to ?1? the corresponding bit in register pnskip (for n = 0,1,2,3). see section ?17. port input/ output? on page 183 for more port i/o co nfiguration details. input voltage right-j ustified adc0h:adc 0l (ad0ljst = 0) left-justified adc0h:adc0l (ad0ljst = 1) vref x 1023/1024 0x03ff 0xffc0 vref x 512/1024 0x0200 0x8000 vref x 256/1024 0x0100 0x4000 0 0x0000 0x0000 input voltage right-justified adc0h:adc0l (ad0ljst = 0) left-justified adc0h:adc0l (ad0ljst = 1) vref x 511/512 0x01ff 0x7fc0 vref x 256/512 0x0100 0x4000 0 0x0000 0x0000 ?vref x 256/512 0xff00 0xc000 ?vref 0xfe00 0x8000 rev. 1.0 49 c8051f360/1/2/3/4/5/6/7/8/9 5.2. temperature sensor the typical temperature sensor transfer function is shown in figure 5.2. the output voltage (v temp ) is the positive adc input when the temperature sensor is selected by bits amx0p4-0 in register amx0p. 0 -50 50 100 (celsius) v temp = slope *(temp c ) + offset mv 700 800 900 1000 1100 (mv) 1200 figure 5.2. typical temperatur e sensor transfer function the uncalibrated temperature sensor output is extrem ely linear and suitable for relative temperature mea - surements (see ta b l e 5.1 for linearity specificatio n s). for absolute temperature measurements, gain and/ or offset calibration is recomme nd ed. typically a 1-point calibration includes the following steps: step 1. control/measure the ambient temper atur e (this temperature must be known). step 2. power the device, and delay for a few seconds to allow for self-heating. step 3. perform an adc conversion with the te mperature sensor selected as the positive input and gnd selected as the negative input. step 4. calculate the offset and/or gain characte ristics, and store these values in non-volatile memory for use with subsequent te mperature sensor measurements. figure 5.3 shows the typical temperature sensor erro r assuming a 1-point calibration at 25 c. note that parameters which affect adc measurement, in particular the voltage reference value, will also a ffect temperature measurement. -40.00 -20.00 0.00 20.00 40.00 60.00 80.00 temperature (degrees c) error (degrees c) -5.00 -4.00 -3.00 -2.00 -1.00 0.00 1.00 2.00 3.00 4.00 5.00 -5.00 -4.00 -3.00 -2.00 -1.00 0.00 1.00 2.00 3.00 4.00 5.00 c8051f360/1/2/3/4/5/6/7/8/9 50 rev. 1.0 figure 5.3. temperature sensor error with 1-point calibration rev. 1.0 51 c8051f360/1/2/3/4/5/6/7/8/9 5.3. modes of operation adc0 has a maximum conversion speed of 200 ksps. the adc0 conversion clock is a divided version of the system clock, determined by the ad0sc bits in the adc0cf register (system clock divided by (ad0sc + 1) for 0 ad0sc 31). 5.3.1. starting a conversion a conversion can be initiated in one of five ways, dep ending on the programmed states of the adc0 start of conversion mode bits (ad0cm2-0) in register a dc0cn. conversions may be initiated by one of the fol - lowing: 1. writing a ?1? to the ad0busy bit of register adc0cn 2. a timer 0 overflow (i.e., timed co ntinuous conversions) 3. a timer 2 overflow 4. a timer 1 overflow 5. a rising edge on the cnvstr input signal 6. a timer 3 overflow writing a ?1? to ad0busy provides software contro l of adc0 whereby conversions are performed "on- demand". during conversion, the ad0busy bit is set to lo gic ?1? and reset to logic ?0? when the conversion is complete. the falling edge of ad0b usy triggers an interrupt (when enabled) and sets the adc0 inter - rupt flag (ad0int). note: when polling for adc conversion completions, the adc0 interrupt flag (ad0int) sho uld be used. converted data is available in th e adc0 data registers, adc0h:adc0l, when bit ad0int is logic ?1?. note that when timer 2 or timer 3 overflows are used as the conversion source, low byte over - flows are used if timer 2/3 is in 8-bit mode; high byte over flows are used if timer 2/3 is in 16-bit mode. see section ?21. timers? on page 247 for timer configuration. important note about using cnvstr: t he cnvstr input pin also functions as port pin p0.7 on the c8051f360 devices and port pin p0.6 on the c8051f 361/2/6/7/8/9 devices. when the cnvstr input is used as the adc0 conversion source, the corresponding port pin should be skipped by the digital cross - bar. to configure the crossbar to ski p the po rt pin, set the appropriate bit to ?1? in register p0skip. see section ?17. port input/output? on page 183 for details on port i/o configuration. c8051f360/1/2/3/4/5/6/7/8/9 52 rev. 1.0 5.3.2. tracking modes according to table 5.1, each adc0 conversion must be prec ed ed by a minimum tracking time for the con - verted result to be accurate. the ad0tm bit in registe r adc0cn controls the adc0 track-and-hold mode. in its default state, the adc0 input is continuously tr acked, except when a conversion is in progress. when the ad0tm bit is logic ?1?, adc0 operates in low-power track-and-hold mode. in this mode, each conver - sion is preceded by a tracking period of 3 sar cloc k s (after the start-of-conversion signal). when the cnvstr signal is used to initiate conversions in low-power tracking mode , adc0 tracks only when cnvstr is low; conversion begins on the rising edge of cnvstr (see figure 5.4 ). tracking can also be disabled (shutdown) when the device is in low power standby or sleep modes. low-power track-and-hold mo de is also useful when amux settings are frequen tly changed, due to the settling time requirements described in section ?5.3.3. settling time requirements? on page 53 . write '1' to ad0busy, timer 0, timer 2, timer 1, timer 3 overflow (ad0cm[2:0]=000, 001,010 011, 101) ad0tm=1 track convert low power mode ad0tm=0 track or convert convert track low power or convert sar clocks 123456789101112 123456789 sar clocks b. adc0 timing for internal trigger source 123456789 cnvstr (ad0cm[2:0]=100) ad0tm=1 a. adc0 timing for external trigger source sar clocks track or convert convert track ad0tm=0 track convert low power mode low power or convert 10 11 13 14 10 11 figure 5.4. 10-bit adc track and conversion example timing rev. 1.0 53 c8051f360/1/2/3/4/5/6/7/8/9 5.3.3. settling time requirements when the adc0 input configuration is changed (i.e., a different amux0 selection is made), a minimum tracking time is required before an accurate conversion can be performed. this tracking time is determined by the amux0 resistance, the adc0 sampling capacita nce, any external source resistance, and the accu - racy required for the conversion. in low-power tracking mode, three sar clocks are used for tracking at the st art of every conversion. for most applications, these three sar clo cks will meet the minimum tracking time requirements. figure 5.5 shows the equivalent adc0 input circuits for b oth differential and single-ended modes. notice that the equivalent time constant for both input circ uit s is the same. the required adc0 settling time for a given settling accuracy (sa) may be approximated by equation 5.1 . when measuring the temperature sensor output or v dd with respect to gnd, r total reduces to r mux . see ta b l e 5.1 for adc0 minimum settling time requirements. equation 5.1. adc0 settling time requirements t 2 n sa ------ - ?? ?? r total c sample where: sa is the settling accuracy, given as a fraction of an lsb (for example, 0.25 to settle within 1/4 lsb) t is the r equired settling time in seconds r total is the sum of the amux0 resistance and any external source resistance. n is the ad c resolution in bits (10). r mux = 5k rc input = r mux * c sample r mux = 5k c sample = 5pf c sample = 5pf mux select mux select differential mode px.x px.x r mux = 5k c sample = 5pf rc input = r mux * c sample mux select single-ended mode px.x figure 5.5. adc0 eq uivalent input circuits c8051f360/1/2/3/4/5/6/7/8/9 54 rev. 1.0 sfr definition 5.1. amx0p: amux0 positive channel select bits 7?5: unused. read = 000b; write = don?t care. bits 4?0: amx0p4?0: amux0 positive input selection sfr page: sfr address: all pages 0xbb r r r r/w r/w r/w r/w r/w reset value ??? amx0p4 amx0p3 amx0p2 amx0p1 amx0p0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 amx0p4-0 adc0 positive input 00000 (1) p1.0 (1) 00001 (1) p1.1 (1) 00010 (1) p1.2 (1) 00011 (1) p1.3 (1) 00100 p1.4 00101 p1.5 00110 p1.6 00111 p1.7 01000 p2.0 01001 p2.1 01010 p2.2 01011 p2.3 01100 p2.4 01101 p2.5 01110 p2.6 01111 p2.7 10000 p3.0 10001 (2) p3.1 (2) 10010 (2) p3.2 (2) 10011 (2) p3.3 (2) 10100 (2) p3.4 (2) 10101?11101 reserved 11110 temp sensor 11111 v dd notes: 1. only applies to c8051f361/2/6/7/8/9 (32-pin and 28-pin); selection reserved on c8051f360 (48-pin) device. 2. only applies to c8051f360/1/6/8 (4 8-pin and 32-pin); selection reserved on c8051f362/7/9 (28-pin) devices. rev. 1.0 55 c8051f360/1/2/3/4/5/6/7/8/9 sfr definition 5.2. amx0n: amux0 negative channel select bits 7?5: unused. read = 000b; write = don?t care. bits 4?0: amx0n4?0: amux0 negative input selection. note that when gnd is selected as the nega tive input, adc0 operates in single-ended mode. for all other negative input select ions, adc0 operates in differential mode. sfr page: sfr address: all pages 0xba r r r r/w r/w r/w r/w r/w reset value ??? amx0n4 amx0n3 amx0n2 am x0n1 amx0n0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 amx0n4-0 adc0 negative input 00000 (1) p1.0 (1) 00001 (1) p1.1 (1) 00010 (1) p1.2 (1) 00011 (1) p1.3 (1) 00100 p1.4 00101 p1.5 00110 p1.6 00111 p1.7 01000 p2.0 01001 p2.1 01010 p2.2 01011 p2.3 01100 p2.4 01101 p2.5 01110 p2.6 01111 p2.7 10000 p3.0 10001 (2) p3.1 (2) 10010 (2) p3.2 (2) 10011 (2) p3.3 (2) 10100 (2) p3.4 (2) 10101?11101 reserved 11110 vref 11111 gnd notes: 1. only applies to c8051f361/2/6/7/8/9 (32-pin and 28-pin); selection reserved on c8051f360 (48-pin) device. 2. only applies to c8051f360/1/6/8 (4 8-pin and 32-pin); selection reserved on c8051f362/7/9 (28-pin) devices. c8051f360/1/2/3/4/5/6/7/8/9 56 rev. 1.0 sfr definition 5.3. adc0cf: adc0 configuration bits 7?3: ad0sc4?0: adc0 sar conversion clock period bits. sar conversion clock is derived from sys tem clock by the following equation, where ad0sc refers to the 5-bit value held in bits ad0sc4?0. sar conversion clock require- ments are given in table 5.1. bit 2: ad0ljst: adc0 left justify select. 0: data in adc0h:adc0l r egisters are right-justified. 1: data in adc0h:adc0l r egisters are left-justified. bits 1?0: unused. read = 00b; write = don?t care. sfr page: sfr address: all pages 0xbc r/w r/w r/w r/w r/w r/w r/w r/w reset value ad0sc4 ad0sc3 ad0sc2 ad0sc1 ad0sc0 ad0ljst ?? 11111000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ad0sc sysclk clk sar --------------------- - 1? = sfr definition 5.4. adc0h: adc0 data word msb bits 7?0: adc0 data word high-order bits. for ad0ljst = 0: bits 7?2 are the sign extension of bit1. bits 1?0 are the upper 2 bits of the 10-bit adc0 data word. for ad0ljst = 1: bits 7?0 are the most-significant bits of the 10-bit adc0 data word. sfr page: sfr address: all pages 0xbe r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr definition 5.5. adc0l: adc0 data word lsb bits 7?0: adc0 data word low-order bits. for ad0ljst = 0: bits 7?0 are the lower 8 bits of the 10-bit data word. for ad0ljst = 1: bits 7?6 are the lower 2 bits of the 10-bit data word. bits 5?0 will always read ?0?. sfr page: sfr address: all pages 0xbd r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rev. 1.0 57 c8051f360/1/2/3/4/5/6/7/8/9 sfr definition 5.6. adc0cn: adc0 control bit 7: ad0en: adc0 enable bit. 0: adc0 disabled. adc0 is in low-power shutdown. 1: adc0 enabled. adc0 is active and ready for data conversions. bit 6: ad0tm: adc0 track mode bit. 0: normal track mode: when adc0 is enabled, tr acking is continuous unless a conversion is in progress. 1: low-power track mode: tracking de fined by ad0cm2-0 bits (see below). bit 5: ad0int: adc0 conversion complete interrupt flag. 0: adc0 has not completed a data conversi on since the last time ad0int was cleared. 1: adc0 has completed a data conversion. bit 4: ad0busy: adc0 busy bit. read: 0: adc0 conversion is complete or a conversion is not currently in progress. ad0int is set to logic ?1? on the falling edge of ad0busy. 1: adc0 conversion is in progress. write: 0: no effect. 1: initiates adc0 conversion if ad0cm2-0 = 000b bit 3: ad0wint: adc0 window compare interrupt flag. 0: adc0 window comparison data match has not occurred since this flag was last cleared. 1: adc0 window comparison data match has occurred. bits 2 ? 0: ad0cm2 ? 0: adc0 start of conversion mode select. when ad0tm = 0: 000: adc0 conversion initiated on every write of ?1? to ad0busy. 001: adc0 conversion initiated on overflow of timer 0. 010: adc0 conversion initiated on overflow of timer 2. 011: adc0 conversion initiated on overflow of timer 1. 100: adc0 conversion initiated on rising edge of external cnvstr. 101: adc0 conversion initiated on overflow of timer 3. 11x: reserved. when ad0tm = 1: 000: tracking initiated on write of ?1? to ad0busy and lasts 3 sar clocks, followed by con- version. 001: tracking initiated on overflow of timer 0 and lasts 3 sar clocks, followed by conversion. 010: tracking initiated on overflow of timer 2 and lasts 3 sar clocks, followed by conversion. 011: tracking initiated on overflow of timer 1 and lasts 3 sar clocks, followed by conversion. 100: adc0 tracks only when cnvstr input is logic low; conversion starts on rising cnvstr edge. 101: tracking initiated on overflow of timer 3 and lasts 3 sar clocks, followed by conversion. 11x: reserved . sfr page: sfr address: all pages 0xe8 (bit addressable) r/w r/w r/w r/w r/w r/w r/w r/w reset value ad0en ad0tm ad0int ad0busy ad0wi nt ad0cm2 ad0cm1 ad0cm0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 c8051f360/1/2/3/4/5/6/7/8/9 58 rev. 1.0 5.4. programmable window detector the adc programmable window detector continuously compares the adc0 output registers to user-pro - grammed limits, and notifies the system when a desired co ndition is detec ted. this is especially effective in an interrupt-driven system, saving code space and cpu ba ndwidth while delivering faster system response times. the window detector interrupt flag (ad0wint in register adc0cn) can also be used in polled mode. the adc0 greater-t han (adc0gth, adc0gtl) and less-than (adc0lth, adc0ltl) reg - isters hold the comparison values. the window detector flag can be programmed to indicate when mea - sured data is inside or outside of the user-program med limits, depending on the contents of the adc0 less-than and adc0 greater-than registers. sfr definition 5.7. adc0gth: adc0 greater-than data high byte bits 7?0: high byte of adc0 greater-than data word. sfr page: sfr address: all pages 0xc4 r/w r/w r/w r/w r/w r/w r/w r/w reset value 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr definition 5.8. adc0gtl: adc0 greater -than dat a low byte bits 7?0: low byte of adc0 greater-than data word. sfr page: sfr address: all pages 0xc3 r/w r/w r/w r/w r/w r/w r/w r/w reset value 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rev. 1.0 59 c8051f360/1/2/3/4/5/6/7/8/9 sfr definition 5.9. adc0lth: adc0 less-than data high byte bits 7?0: high byte of adc0 less-than data word. sfr page: sfr address: all pages 0xc6 r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr definition 5.10. adc0ltl: adc0 less-than data low byte bits 7?0: low byte of adc0 less-than data word. sfr page: sfr address: all pages 0xc5 r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 c8051f360/1/2/3/4/5/6/7/8/9 60 rev. 1.0 5.4.1. window detector in single-ended mode figure 5.6 shows two example window comparisons fo r r ight-justified, single-ended data, with adc0lth:adc0ltl = 0x0080 (128d) and adc0gth:adc0gtl = 0x0040 (64d). in single-ended mode, the input voltage can range from ?0? to vref x (1023/ 1024) with respect to gnd, and is represented by a 10-bit unsigned intege r value. in the left example, an ad0win t interrupt will be gener ated if the adc0 conversion word (adc0h:adc0l) is within the range defined by adc0gth:adc0gtl and adc0lth:adc0ltl (if 0x0040 < adc0h:adc0l < 0x0080). in the right example, and ad0wint interrupt will be generated if the adc0 conversion word is out side of t he range defined by the adc0gt and adc0lt registers (if adc0h:adc0l < 0x0040 or adc0h:adc0l > 0x0080). figure 5.7 shows an exam - ple using left-justified data with the same comparison values. 0x03ff 0x0081 0x0080 0x007f 0x0041 0x0040 0x003f 0x0000 0 input voltage (px.x - gnd) vref x (1023/1024) vref x (128/1024) vref x (64/1024) ad0wint=1 ad0wint not affected ad0wint not affected adc0lth:adc0ltl adc0gth:adc0gtl 0x03ff 0x0081 0x0080 0x007f 0x0041 0x0040 0x003f 0x0000 0 input voltage (px.x - gnd) vref x (1023/1024) vref x (128/1024) vref x (64/1024) ad0wint not affected ad0wint=1 ad0wint=1 adc0h:adc0l adc0h:adc0l adc0gth:adc0gtl adc0lth:adc0ltl 0xffc0 0x2040 0x2000 0x1fc0 0x1040 0x1000 0x0fc0 0x0000 0 input voltage (px.x - gnd) vref x (1023/1024) vref x (128/1024) vref x (64/1024) ad0wint=1 ad0wint not affected ad0wint not affected adc0lth:adc0ltl adc0gth:adc0gtl 0xffc0 0x2040 0x2000 0x1fc0 0x1040 0x1000 0x0fc0 0x0000 0 input voltage (px.x - gnd) vref x (1023/1024) vref x (128/1024) vref x (64/1024) ad0wint not affected ad0wint=1 ad0wint=1 adc0h:adc0l adc0h:adc0l adc0lth:adc0ltl adc0gth:adc0gtl figure 5.6. adc window co mpare example: right-justified single-ended data figure 5.7. adc window co mp are example: left-justified single-ended data rev. 1.0 61 c8051f360/1/2/3/4/5/6/7/8/9 5.4.2. window detector in differential mode figure 5.8 shows two example window comparisons for r ight-justified, differential data, with adc0lth:adc0ltl = 0x0040 (+64d) and adc0gth:adc0gth = 0xffff (-1d). in differential mode, the me asurable voltage between the input pins is between -vref and vref*(511/512). output codes are rep - resented as 10-bit 2?s complement s igned integers. in the left example, an ad 0wint interrupt will be gen - erated if the adc0 conversion word (adc0h:adc0l) is within the range defined by adc0gth:adc0gtl and adc0lth:adc0ltl (if 0xffff (-1d) < adc0h:adc0l < 0x0040 (64d)). in the ri g ht example, an ad0wint interrupt will be generated if the adc0 conversion word is ou tside of the range defined by the adc0gt and adc0lt registers (if adc0h:adc0l < 0xffff (-1d) or adc0h:adc0l > 0x0040 (+64d)). figure 5.9 shows an example using left-justified d ata with the same comparison values. 0x01ff 0x0041 0x0040 0x003f 0x0000 0xffff 0xfffe 0x0200 -vref input voltage (px.x - px.x) vref x (511/512) vref x (64/512) vref x (-1/512) 0x01ff 0x0041 0x0040 0x003f 0x0000 0xffff 0xfffe 0x0200 -vref input voltage (px.x - px.x) vref x (511/512) vref x (64/512) vref x (-1/512) ad0wint=1 ad0wint not affected ad0wint not affected adc0lth:adc0ltl adc0gth:adc0gtl ad0wint not affected ad0wint=1 ad0wint=1 adc0h:adc0l adc0h:adc0l adc0gth:adc0gtl adc0lth:adc0ltl 0x7fc0 0x1040 0x1000 0x0fc0 0x0000 0xffc0 0xff80 0x8000 -vref input voltage (px.x - px.y) vref x (511/512) vref x (64/512) vref x (-1/512) 0x7fc0 0x1040 0x1000 0x0fc0 0x0000 0xffc0 0xff80 0x8000 -vref input voltage (px.x - px.x) vref x (511/512) vref x (64/512) vref x (-1/512) ad0wint=1 ad0wint not affected ad0wint not affected adc0lth:adc0ltl adc0gth:adc0gtl ad0wint not affected adc0gth:adc0gtl ad0wint=1 ad0wint=1 adc0h:adc0l adc0h:adc0l adc0lth:adc0ltl figure 5.8. ad c window compare example: righ t-justified differential data figure 5.9. adc window compare exampl e: lef t-justified differential data table 5.1. adc0 electrical characteristics v dd = 3.0 v, vref = 2.40 v (refsl=0), ?40 to +85 c unless otherwise specified. parameter conditions min typ max units dc accuracy resolution integral nonlinearity differential nonlinearity offset error full scale error dynamic performance (10 khz sine-wave single-ended input, 0 to 1 db below full scale, 200 ksps) signal-to-noise plus distortion total harmonic distortion spurious-free dynamic range conversion rate sar conversion clock conversion time in sar clocks track/hold acquisition time throughput rate analog inputs adc input voltage range absolute pin voltage with res pect to gnd input capacitance temperature sensor linearity* slope slope error* offset offset error* power specifications power supply current (v dd supplied to adc0) power supply rejection *note: represents one standard deviation from the mean. incl udes adc offset, gain, and linearity variations. c8051f360/1/2/3/4/5/6/7/8/9 62 rev. 1.0 10 bits ?0.51lsb guaranteed monotonic ? 0.5 1 lsb ?12 3 12 lsb differential mode ?5 1 5 lsb 53 58 ? db up to the 5 th harmonic ??75?db ?75?db ?? 3mhz 13 ? ? clocks 300 ? ? ns ? ? 200 ksps single ended (ain+ ? gnd) dif ferential (ain+ ? ain?) 0 ?vref ? ? vref vref v v single ended or differential 0 ? v dd v ?5?pf ?0.2?c ? 2.18 ? mv/oc ? 172 ? v/oc (temp = 0 c) ? 802 ? mv ?18.5?mv operating mode, 200 ksps ? 450 900 a ?3?mv/v rev. 1.0 63 c8051f360/1/2/3/4/5/6/7/8/9 6. 10-bit current mode dac (i da0, c8051f360/1/2/6/7/8/9) the c8051f360/1/2/6/7/8/9 devices include a 10-bit current-mode digital-to-analog converter (idac). the maximum current output of the idac can be ad justed for three different current settings; 0.5 ma, 1 ma, and 2 ma. the idac is enabled or disabled with the ida0en bit in the ida0 control register (see sfr definition 6.1 ). when ida0en is set to ?0?, the idac po rt pin (p0.4 for c8051f360, p0.1 for c8051f361/2/6/7/8/9) behaves as a normal gpio pin. when ida0en is set to ?1?, the digital output drivers and weak pullup for the idac pin are automatically dis abled, and the pin is connected to the idac output. an internal bandgap bias generator is used to generate a reference current for the idac whenever it is enabled. when using the idac, the appropriate bit in th e p0skip register should be set to ?1? to force the crossbar to skip the idac pin. 6.1. ida0 output scheduling ida0 features a flexible output update mechanism which allows for seamless full-scale changes and sup - ports jitter-free updates for wavefo rm g eneration. three update modes are provided, allowing idac output updates on a write to ida0h, on a time r overflow, or on an external pin edge. 6.1.1. update output on-demand in its default mode (ida0cn.[6:4] = ?111?) the ida0 output is updated ?on-demand? on a write to the high- byte of the ida0 data register (ida0h). it is important to note that writes to ida0l are held in this mode, and have no effect on the ida0 output until a write to ida0h takes place. if writing a full 10-b it word to the idac data registers, the 10-bit data word is written to the low byte (ida0l) and high byte (ida0h) data reg - isters. dat a is latched into ida0 after a write to the ida0h register, so the write sequence should be ida0l followed by ida0h if the full 10-bit resolution is required. the idac can be used in 8-bit mode by initializing ida0l to the desired va lue (typically 0x00), and writ ing data to only ida0h (see section 6.2 for information on the format of the 10-bit idac d ata word within the 16-bit sfr space). ida0 10 ida0 ida0cn ida0en ida0cm2 ida0cm1 ida0cm0 ida0omd1 ida0omd0 ida0h ida0l latch 8 2 ida0h timer 0 timer 1 timer 2 timer 3 cnvstr figure 6.1. ida0 functional block diagram c8051f360/1/2/3/4/5/6/7/8/9 64 rev. 1.0 6.1.2. update output based on timer overflow similar to the adc operation, in which an adc conv ersion can be initiated by a timer overflow indepen - dently of the processor, the idac outputs can use a t imer overflow to schedule an output update event. this feature is useful in systems where the idac is used to generate a waveform of a defined sampling rate by eliminating the effects of variable interrupt la tency and instruction execution on the timing of the idac output. when the ida0cm bits (ida0cn.[6:4]) are se t to ?000?, ?001?, ?010? or ?011?, writes to both idac data registers (ida0l and ida0h) are held until an associated timer overflow event (timer 0, ti mer 1, timer 2 or timer 3, respectively) occurs, at which time the ida0h:ida0l contents are copied to the idac input latches, a llowing the idac output to change to the new value. 6.1.3. update output based on cnvstr edge the idac output can also be configured to update on a rising edge, falling edge, or both edges of the external cnvstr signal. when the ida0cm bits (ida0cn.[6:4]) are set to ?100?, ?101?, or ?110?, writes to both idac data registers (ida0l and ida0h) are held until an edge occurs on the cnvstr input pin. the particular setting of the ida0cm bits determines whether idac outputs are updated on ri sing, falling, or both edges of cnvstr. when a corresponding edge oc curs, the ida0h:ida0l contents are copied to the idac input latches, allowing the idac output to change to the new value. 6.2. idac output mapping the idac data registers (ida0h and ida0l) are left-j ustified, meaning that the eight msbs of the idac output word are mapped to bits 7 ? 0 of the ida0h register, and the two lsbs of the idac output word are mapped to bits 7 and 6 of the ida0l register. the data word mapping for the idac is shown in figure 6.2 . ida0h ida0l d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 input data word (d9?d0) output current ida0omd[1:0] = ?1x? output current ida0omd[1:0] = ?01? output current ida0omd[1:0] = ?00? 0x000 0 ma 0 ma 0 ma 0x001 1/1024 x 2 ma 1/1024 x 1 ma 1/1024 x 0.5 ma 0x200 512/1024 x 2 ma 512/1024 x 1 ma 512/1024 x 0.5 ma 0x3ff 1023/1024 x 2 ma 1023/1024 x 1 ma 1023/1024 x 0.5 ma figure 6.2. ida0 data word mapping the full-scale output current of the idac is selected using the ida0omd bits (ida0cn[1:0]). by default, the idac is set to a full-scale output current of 2 ma. the ida0omd bits can also be configured to provide full- scale output currents of 1 ma or 0.5 ma, as shown in sfr definition 6.1 . rev. 1.0 65 c8051f360/1/2/3/4/5/6/7/8/9 sfr definition 6.1. ida0cn: ida0 control bit 7: ida0en: ida0 enable. 0: ida0 disabled. 1: ida0 enabled. bits 6 ? 4: ida0cm[2:0]: ida0 updat e source select bits. 000: dac output updates on timer 0 overflow. 001: dac output updates on timer 1 overflow. 010: dac output updates on timer 2 overflow. 011: dac output updates on timer 3 overflow. 100: dac output updates on rising edge of cnvstr. 101: dac output updates on falling edge of cnvstr. 110: dac output updates on any edge of cnvstr. 111: dac output updates on write to ida0h. (default) bits 3 ? 2: unused. read = 00b. write = don?t care. bits 1?0: ida0omd[1:0]: ida0 output mode select bits. 00: 0.5 ma full-scale output current. 01: 1.0 ma full-scale output current. 1x: 2.0 ma full-scale output current. (default) sfr page: sfr address: all pages 0xb9 r/w r/w r/w r/w r r r/w r/w reset value ida0en ida0cm ?? ida0omd 01110010 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr definition 6.2. ida0h: ida0 data word msb bits 7 ? 0: ida0 data word high-order bits. bits 7 ? 0 are the most-significant bits of the 10-bit ida0 data word. sfr page: sfr address: all pages 0x97 r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 c8051f360/1/2/3/4/5/6/7/8/9 66 rev. 1.0 sfr definition 6.3. ida0l: ida0 data word lsb bits 7 ? 6: ida0 data word low-order bits. lower 2 bits of the 10-bit data word. bits 5 ? 0: unused. read = 000000b, write = don?t care. sfr page: sfr address: all pages 0x96 r / wr / wrrrrrrr e s e t v a l u e ? ? ? ? ? ? 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 table 6.1. idac electrical characteristics ? 40 to +85 c, v dd = 3.0 v full-scale output current set to 2 ma unless otherwise specified. parameter conditions min typ max units static performance resolution 10 bits integral nonlinearity ? 0.5 2 lsb differential nonlinearity guaranteed monotonic ? 0.5 1 lsb output compliance range ? ? v dd ? 1.2 v offset error ? 0 ? lsb full scale error 2 ma full scale output current ?15 0 15 lsb full scale error tempco ? 30 ? ppm/c v dd power supply rejection ratio ? 6.5 ? a/v dynamic performance output settling time to 1/2 lsb ida0h:l = 0x3ff to 0x000 ? 5 ? s startup time ? 5 ? s gain variation 1 ma full scale output current 0.5 ma full scale output current ? ? 1 1 ? ? % % power consumption power supply current (v dd supplied to idac) 2 ma full scale output current 1 ma full scale output current 0.5 ma full scale output current ? ? ? 2140 1140 640 ? ? ? a a a rev. 1.0 67 c8051f360/1/2/3/4/5/6/7/8/9 7. voltage reference (c8051f360/1/2/6/7/8/9) the voltage reference mux on the c8051f360/1/2/6/7/ 8/9 devices is configurable to use an externally connected voltage reference, the internal reference voltage generator, or the v dd power supply voltage (see figure 7.1 ). the refsl bit in the reference control register (ref0cn) selects the reference source. for an external source or the internal reference, refsl should be set to ?0?. to use v dd as the reference source, refsl should be set to ?1?. the biase bit enables th e internal vol tage bi as generator, which is used by the adc, temperature sensor, internal oscillators, and current dac. this bias is enabled when any of the aforementioned peripherals are enabled. the bias g enerator may be enabl ed manually by writing a ?1? to the biase bit in register ref0cn; see sfr definition 7.1 for ref0cn register details. the elec trical specifications for the v oltage reference circuit are given in ta b l e 7.1 . the internal voltage reference circuit consists of a 1.2 v, temperature stable bandgap voltage reference g enerator and a gain-of-two output buffer amplifier. the internal voltage reference can be driven out on the vref pin by setting the refbe bit in register ref0cn to a ?1? (see sfr definition 7.1 ). the maximum load seen by the vref pin must be less than 200 a to gnd. when using the internal voltage reference, by pass capacitors of 0.1 f and 4.7 f are recommended from the vref pin to gnd. if the internal refer - ence is not used, the refbe bit should be cleared to ?0 ?. electrical s pecifications for the internal voltage reference are given in table 7.1 . important note about the vref pin: po rt pin p0.3 on the c8051f360 device and p0.0 on c8051f361/2/6/7/89 devices is used as the external vref input and as an output for the internal vref. when using either an external voltage reference or the internal reference circuitry, the port pin should be configured as an analog pin, and skipped by the digital crossbar. to co nfigure the port pin as an analog pin, set the appropriate bit to ?0? in register p0mdin. to configure the crossbar to skip the vref port pin, set the appropriate bit to ?1? in register p0skip. refer to section ?17. port input/output? on page 183 for vref (to adc) to analog mux vdd vref r1 vdd external voltage reference circuit gnd temp sensor en bias generator to adc, idac, internal oscillators en iosce n 0 1 ref0cn refsl tempe biase refbe refbe internal reference en recommended bypass capacitors + 4.7 f0.1 f figure 7.1. voltage refere nce functional block diagram c8051f360/1/2/3/4/5/6/7/8/9 68 rev. 1.0 complete port i/o configur ation details. the tempe bit in register ref0cn enables/disables the tempera - ture sensor. while disabled, the temperature sensor de faults to a high impedance state and any adc0 measurements performed on the sensor result in meaningless data. sfr definition 7.1. ref0cn: reference control bits 7?4: unused. read = 0000b; write = don?t care. bit 3: refsl: voltage reference select. this bit selects the source for the internal voltage reference. 0: vref pin used as voltage reference. 1: v dd used as voltage reference. bit 2: tempe: temperature sensor enable bit. 0: internal temperature sensor off. 1: internal temperature sensor on. bit 1: biase: internal analog bias generator enable bit. 0: internal bias generator off. 1: internal bias generator on. bit 0: refbe: internal refe rence buffer enable bit. 0: internal reference buffer disabled. 1: internal reference buffer enabled. internal voltage reference driven on the vref pin. sfr page: sfr address: all pages 0xd1 r r r r r/w r/w r/w r/w reset value ???? refsl tempe biase refbe 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 table 7.1. voltage reference electrical characteristics v dd = 3.0 v; ?40 to +85 c unless otherwise specified. parameter conditions min typ max units internal reference (refbe = 1) output voltage 25 c ambient 2.35 2.42 2.50 v vref short-circuit current ? ? 10 ma vref temperature coefficient ? 25 ? ppm/c load regulation load = 0 to 200 a to agnd ? 3 ? v/a vref turn-on time 1 4.7 f tantalum, 0.1 f ceramic byp ass ? 7.5 ? ms vref turn-on time 2 0.1 f ceramic bypass ? 200 ? s power supply rejection ? 1.4 ? mv/v external reference (refbe = 0) input voltage range 0 ? v dd v input current sample rate = 200 ksps; vref = 3.0 v ? 3 ? a power specifications adc bias generator biase = ?1? or ad0en = ?1? or ioscen = ?1? ? 100 150 a reference bias generator refbe = ?1? or tempe = ?1? or ida0en = ?1? ? 30 50 a rev. 1.0 69 c8051f360/1/2/3/4/5/6/7/8/9 c8051f360/1/2/3/4/5/6/7/8/9 70 rev. 1.0 8. comparators c8051f36x devices include two on-chip programmable voltage comparators, comparator0 and comparator1, shown in figure 8.1 and figure 8.2 ( note: th e port pin comparator inputs differ between c8051f36x devices. the first port i/o p in shown is for c8051f360/3 devices). the comparators offer programmable response time a nd hysteresis, an analog input multiplexer, and two outputs that are optionally available at the port pins: a synchronous ?lat ched? output (cp0 and cp1), or an asynchronous ?raw? output (cp0a and cp1a). the a synchronous cp0a and cp1a signals are available even when the system clock is not active. this allows the comparators to operate and generate an output with the device in stop mode. when assigned to a po rt pin, the comparator outputs may be configured as open drain or push-pull (see section ?17.2. port i/o initializ a tion? on page 187 ). comparator0 may also be used as a reset source (see section ?12.5. comparator0 reset? on page 131 ). the comparator inputs are selected in the cpt0mx and cpt1mx registers (sfr definition 8.2 and sfr definition 8.5 ). the cmxnp1 ? c mxnp0 bits select the comparator positive input; the cmxnn1 ? cmxnn0 bits select the comparator negative input. important note about comparator inputs: the port pins selected as comparator inputs should be con - figured as analog inputs in their associated port co nfigur ation register, and configured to be skipped by the crossbar (for details on port configuration, see section ?17.3. general purpose port i/o? on page 190 ). vdd cpt0cn reset decision tree + - crossbar q q set clr d q q set clr d (synchronizer) gnd cp0 + cp0 - cp0en cp0out cp0rif cp0fif cp0hyp1 cp0hyp0 cp0hyn1 cp0hyn0 cpt0mx cmx0n3 cmx0n2 cmx0n1 cmx0n0 cmx0p1 cmx0p0 cpt0md cp0rie cp0fie cp0md1 cp0md0 cp0 cp0a cp0 interrupt 0 1 0 1 cp0rif cp0fif 0 1 cp0en 0 1 ea p1.5 / p1.1 p2.4 / p1.5 p3.2 / p2.1 p3.6 / p2.5 p1.4 / p1.0 p2.3 / p1.4 p3.1 / p2.0 p3.5 / p2.4 figure 8.1. comparator0 functional block diagram vdd cpt1cn + - crossbar q q set clr d q q set clr d (synchronizer) gnd cp1 + cp1 - cpt1mx cp1 cp1a cp1 interrupt 0 1 0 1 cp1rif cp1fif 0 1 cp1en 0 1 ea p2.1 / p1.3 p2.6 / p1.7 p3.4 / p2.3 p4.0 / p2.7 p2.0 / p1.2 p2.5 / p1.6 p3.3 / p2.2 p3.7 / p2.6 cmx1n0 cmx1p1 cmx1p0 cmx1n1 cp1en cp1out cp1rif cp1fif cp1hyp1 cp1hyp0 cp1hyn1 cp1hyn0 cpt1md cp1rie cp1fie cp1md1 cp1md0 rev. 1.0 71 c8051f360/1/2/3/4/5/6/7/8/9 figure 8.2. comparator1 functional block diagram a comparator output can be polled in software, used as an interrupt source, and/or routed to a port pin. when routed to a port pin, the comparator outputs are available asynchronous or synchronous to the sys - tem clock; the asynchronous outputs are available ev en in stop mode (with no system clock active). when disabled, the comparator outputs (if assigned to a port i/o pin via the crossbar) default to the logic low state, and their supply current falls to less than 100 na. see section ?17.1. priority crossbar decoder? on page 185 for details on configuring comparator outputs via the digital crossbar. comparator inputs can be externally driven from ?0.25 v to (v dd ) + 0.25 v without damage or upset. the complete comparator e lectrical specifications are given in ta b l e 8.1 . the comparator response time may be configured in software via the cpt0md and cpt1md registers (s ee sfr definition 8.3 and sfr definition 8.6 ). selecting a longer response time reduces the comparator supply current. see ta b l e 8.1 for complete timing and power consumption specifications. positive hysteresis voltage (programmed with cp0hyp bits) negative hysteresis voltage (programmed by cp0hyn bits) vin- vin+ inputs circuit configuration + _ cp0+ cp0- cp0 vin+ vin- out v oh positive hysteresis disabled maximum positive hysteresis negative hysteresis disabled maximum negative hysteresis output v ol c8051f360/1/2/3/4/5/6/7/8/9 72 rev. 1.0 figure 8.3. compar ator hysteresis plot the comparator hysteresis is software-programmable via the comparator control registers cpt0cn and cpt1cn. the user can program both the amount of hyst eresis voltage (referred to the input voltage) and the positive and negative-going symmetry of th is hysteresis around the threshold voltage. the comparator hysteresis is programmed using bits3 ? 0 in the comparator co ntrol registers cpt0cn and cpt1cn (shown in sfr definition 8.1 and sfr definition 8.4 ). the amount of neg ative hysteresis voltage is determined by the settings of the cp0hyn an d cp1hyn bits. as shown in figure 8.3 , settings of 20, 10 or 5 mv of negative hysteresis can be programmed, or negative hysteresis can be disabled. in a similar way, the amount of positive hysteresis is determined by the setting the cp0hyp and cp1hyp bits. comparator interrupts can be genera ted on both rising-e dge and falling-edge output transitions. (for inter - rupt enable and priority control, see section ?10. interrupt handler? on page 107 ). the cp0fif or cp1fif flag is set to logic ?1? upon a comp arator falling-edge occurren ce, and the cp 0rif or cp1rif flag is set to logic ?1? upon the comparator rising-edge occurrence. on ce set, these bits remain set until cleared by soft - ware. the comparator rising-edge interrupt mask is ena bled by setting cp0rie or cp1rie to a logic ?1?. the comparator falling-edge interrupt mask is enabled by setting cp0fie or cp1fie to a logic ?1?. the output state of the comparator can be obtained at a ny time by reading the cp0out or cp1out bit. the comparator is enabled by setting the cp0en or cp1en bit to logic ?1?, and is disabled by clearing this bit to logic ?0?. note that false rising ed ges and falling edges can be detected when the comparator is fi rst powered on or if changes are made to the hy steresis or response time control bits. therefore, it is recommended that the rising-edge and falling-edge flags be explicitly cleared to logic ?0? a short time after the comparator is enabled or its mode bits have been changed. this power up time is specified in ta b l e 8.1 on page 79 . rev. 1.0 73 c8051f360/1/2/3/4/5/6/7/8/9 sfr definition 8.1. cpt0cn: comparator0 control bit 7: cp0en: comparator0 enable bit. 0: comparator0 disabled. 1: comparator0 enabled. bit 6: cp0out: comparator0 output state flag. 0: voltage on cp0+ < cp0 ? . 1: voltage on cp0+ > cp0 ? . bit 5: cp0rif: comparator0 rising-edge flag. must be cleared by software. 0: no comparator0 rising edge has occurr ed since this flag was last cleared. 1: comparator0 rising edge has occurred. bit 4: cp0fif: comparator0 falling-edge flag. must be cleared by software. 0: no comparator0 falling-e dge has occurred since this flag was last cleared. 1: comparator0 falling-edge has occurred. bits 3 ? 2: cp0hyp1 ? 0: comparator0 positive hysteresis control bits. 00: positive hysteresis disabled. 01: positive hysteresis = 5 mv. 10: positive hysteresis = 10 mv. 11: positive hysteresis = 20 mv. bits 1 ? 0: cp0hyn1 ? 0: comparator0 negative hysteresis control bits. 00: negative hysteresis disabled. 01: negative hysteresis = 5 mv. 10: negative hysteresis = 10 mv. 11: negative hysteresis = 20 mv. sfr page: sfr address: all pages 0x9b r/w r r/w r/w r/w r/w r/w r/w reset value cp0en cp0out cp0rif cp0fif cp0hyp1 cp0hyp0 cp0hyn1 cp0hyn0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 c8051f360/1/2/3/4/5/6/7/8/9 74 rev. 1.0 sfr definition 8.2. cpt0mx: comparator0 mux selection bits 7 ? 6: unused. read = 11b, write = don?t care. bits 5 ? 4: cmx0n1 ? cmx0n0: comparator0 negative input mux select. these bits select which port pin is us ed as the comparator0 negative input. bits 3 ? 2: unused. read = 11b, write = don?t care. bits 1 ? 0: cmx0p3 ? cmx0p0: comparator0 positive input mux select. these bits select which port pin is us ed as the comparator0 positive input. sfr page: sfr address: all pages 0x9f r/w r/w r/w r/w r/w r/w r/w r/w reset value ?? cmx0n1 cmx0n0 ?? cmx0p1 cmx0p0 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 cmx0n1 cmx0n0 c8051f360/3 c8051f361/2/4/5/6/7/8/9 negative input negative input 0 0 p1.5 p1.1 0 1 p2.4 p1.5 1 0 p3.2 p2.1 1 1 p3.6 p2.5 cmx0p1 cmx0p0 c8051f360/3 c8051f361/2/4/5/6/7/8/9 positive input positive input 00 p1.4 p1.0 01 p2.3 p1.4 10 p3.1 p2.0 11 p3.5 p2.4 rev. 1.0 75 c8051f360/1/2/3/4/5/6/7/8/9 sfr definition 8.3. cpt0md: comparator 0 mode selection bits 7 ? 6: unused. read = 00b, write = don?t care. bit 5: cp0rie: comparator0 rising-edge interrupt enable. 0: comparator0 rising-edge interrupt disabled. 1: comparator0 rising-edge interrupt enabled. bit 4: cp0fie: comparator0 falling-edge interrupt enable. 0: comparator0 falling-edge interrupt disabled. 1: comparator0 falling-edge interrupt enabled. bits 3 ? 2: unused. read = 00b, write = don?t care. bits 1 ? 0: cp0md1 ? cp0md0: comparator0 mode select these bits select the response time for comparator0. sfr page: sfr address: all pages 0x9d r r r/w r/w r r r/w r/w reset value ?? cp0rie cp0fie ?? cp0md1 cp0md0 00000010 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 mode cp0md1 cp0md0 cp0 response time (typ) 000 100 ns 101 175 ns 210 320 ns 3 1 1 1050 ns c8051f360/1/2/3/4/5/6/7/8/9 76 rev. 1.0 sfr definition 8.4. cpt1cn: comparator1 control bit 7: cp1en: comparator1 enable bit. 0: comparator1 disabled. 1: comparator1 enabled. bit 6: cp1out: comparator1 output state flag. 0: voltage on cp1+ < cp1 ? . 1: voltage on cp1+ > cp1 ? . bit 5: cp1rif: comparator1 rising-edge flag. must be cleared by software. 0: no comparator1 rising edge has occurr ed since this flag was last cleared. 1: comparator1 rising edge has occurred. bit 4: cp1fif: comparator1 falling-edge flag. must be cleared by software. 0: no comparator1 falling-e dge has occurred since this flag was last cleared. 1: comparator1 falling-edge has occurred. bits 3 ? 2: cp1hyp1 ? 0: comparator1 positive hysteresis control bits. 00: positive hysteresis disabled. 01: positive hysteresis = 5 mv. 10: positive hysteresis = 10 mv. 11: positive hysteresis = 20 mv. bits 1 ? 0: cp1hyn1 ? 0: comparator1 negative hysteresis control bits. 00: negative hysteresis disabled. 01: negative hysteresis = 5 mv. 10: negative hysteresis = 10 mv. 11: negative hysteresis = 20 mv. sfr page: sfr address: all pages 0x9a r/w r r/w r/w r/w r/w r/w r/w reset value cp1en cp1out cp1rif cp1fif cp1hyp1 cp1hyp0 cp1hyn1 cp1hyn0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rev. 1.0 77 c8051f360/1/2/3/4/5/6/7/8/9 sfr definition 8.5. cpt1mx: comparator1 mux selection bits 7 ? 6: unused. read = 11b, write = don?t care. bits 5 ? 4: cmx1n1 ? cmx1n0: comparator1 negative input mux select. these bits select which port pin is us ed as the comparator1 negative input. bits 3 ? 2: unused. read = 11b, write = don?t care. bits 1 ? 0: cmx1p1 ? cmx1p0: comparator1 positive input mux select. these bits select which port pin is us ed as the comparator1 positive input. sfr page: sfr address: all pages 0x9e r/w r/w r/w r/w r/w r/w r/w r/w reset value ?? cmx1n1 cmx1n0 ?? cmx1p1 cmx1p0 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 cmx1n1 cmx1n0 c8051f360/3 c8051f361/2/4/5/6/7/8/9 negative input negative input 0 0 p2.1 p1.3 0 1 p2.6 p1.7 1 0 p3.4 p2.3 1 1 p4.0 p2.7 cmx1p1 cmx1p0 c8051f360/3 c8051f361/2/4/5/6/7/8/9 positive input positive input 00 p2.0 p1.2 01 p2.5 p1.6 10 p3.3 p2.2 11 p3.7 p2.6 c8051f360/1/2/3/4/5/6/7/8/9 78 rev. 1.0 sfr definition 8.6. cpt1md: comparator 1 mode selection bits 7 ? 6: unused. read = 00b, write = don?t care. bit 5: cp1rie: comparator1 rising-edge interrupt enable. 0: comparator1 rising-edge interrupt disabled. 1: comparator1 rising-edge interrupt enabled. bit 4: cp1fie: comparator1 falling-edge interrupt enable. 0: comparator1 falling-edge interrupt disabled. 1: comparator1 falling-edge interrupt enabled. bits 3 ? 2: unused. read = 00b, write = don?t care. bits 1 ? 0: cp1md1 ? cp1md0: comparator1 mode select these bits select the response time for comparator1. sfr page: sfr address: all pages 0x9c r r r/w r/w r r r/w r/w reset value ?? cp1rie cp1fie ?? cp1md1 cp1md0 00000010 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 mode cp1md1 cp1md0 cp1 response time (typ) 0 0 0 100 ns 1 0 1 175 ns 2 1 0 320 ns 3 1 1 1050 ns table 8.1. comparator electrical characteristics v dd = 3.0 v, ?40 to +85 c unless otherwise noted. parameter conditions min typ max units response time: mode 0, vcm * = 1.5 v cpx+ ? cpx? = 100 mv ? 100 ? ns cpx+ ? cpx? = ?100 mv ? 250 ? ns response time: mode 1, vcm * = 1.5 v cpx+ ? cpx? = 100 mv ? 175 ? ns cpx+ ? cpx? = ?100 mv ? 500 ? ns response time: mode 2, vcm * = 1.5 v cpx+ ? cpx? = 100 mv ? 320 ? ns cpx+ ? cpx? = ?100 mv ? 1100 ? ns response time: mode 3, vcm * = 1.5 v cpx+ ? cpx? = 100 mv ? 1050 ? ns cpx+ ? cpx? = ?100 mv ? 5200 ? ns common-mode rejection ratio ? 1.26 5 mv/v positive hysteresis 1 cpxhyp1?0 = 00 ? 0 1 mv positive hysteresis 2 cpxhyp1?0 = 01 1 5 10 mv positive hysteresis 3 cpxhyp1?0 = 10 6 10 20 mv positive hysteresis 4 cpxhyp1?0 = 11 12 20 30 mv negative hysteresis 1 cpxhyn1?0 = 00 ? 0 1 mv negative hysteresis 2 cpxhyn1?0 = 01 1 5 10 mv negative hysteresis 3 cpxhyn1?0 = 10 6 10 20 mv negative hysteresis 4 cpxhyn1?0 = 11 12 20 30 mv inverting or non- inverting input v oltage range ?0.25 ? v dd + 0.25 v input capacitance ? 4 ? pf input bias current ? 0.001 ? na input offset voltage ?5 ? +5 mv power supply power supply rejection ? 0.3 ? mv/v power-up time ? 10 ? s supply current at dc mode 0 ? 11.4 20 a mode 1 ? 4.6 10 a mode 2 ? 1.9 5 a mode 3 ? 0.4 2.5 a *note: vcm is the common-mode voltage on cpx+ and cpx?. rev. 1.0 79 c8051f360/1/2/3/4/5/6/7/8/9 c8051f360/1/2/3/4/5/6/7/8/9 80 rev. 1.0 9. cip-51 microcontroller the mcu system controller core is the cip-51 microcon troller. the cip-51 is fully compatible with the mcs-51? instruction set; standard 803x/805x assemble rs and compilers can be used to develop soft - ware. the mcu family has a superset of all the peripherals included with a standard 8051. included are five 1 6-bit counter/timers (see description in section 21 ), one full-duplex uart (see description in section 19 ), 256 bytes of internal ram, 128 byte special function regist e r (sfr) address space (see section 9.4.6 ), and up to four byte-wide and one 7-bit-wide i/o ports (see description in section 17 ). the cip-51 also includes on-chip debug hardware (see description in section 24 ), and interfaces directly with the mcu?s analog and digital subsystems pr ov iding a complete data acquisiti on or control-system solution in a single integrated circuit. the cip-51 microcontroller core implements the standard 8051 organization and peripherals as well as additional c ustom peripherals and func tions to extend its capability (see figure 9.1 for a block diagram). the cip-51 includes the following features: 9.1. performance the cip-51 employs a pipelined architecture that grea tly increases its instruction throughput over the stan - dard 8051 architecture. in a standar d 8051, all inst ructions except for mul and div take 12 or 24 system clock cycles to execute, and usually have a maximum system clock of 12 mhz. by contrast, the cip-51 core exec utes 70% of its instructions in one or tw o system clock cycles, with no instructions taking more than eight system clock cycles. with the cip-51's system clock running at 100 mhz, it ha s a peak throughput of 100 mips. the cip-51 has a total of 109 instructions. the table below shows the total number of instructions that require each execution time. clocks to execute 1 2 2/3 3 3/4 4 4/5 5 8 number of instructions 26 50 5 14 7 3 1 2 1 - fully compatible wit h mcs-51 instruction set - 100 or 50 mips peak using the on-chip pll - 256 bytes of internal ram - 8/4 byte-wide i/o ports - extended interrupt handler - reset input - power management modes - on-chip debug logic data bus tmp1 tmp2 prgm. address reg. pc incrementer alu psw data bus data bus memory interface mem_address d8 pipeline buffer data pointer interrupt interface system_irqs emulation_irq mem_control control logic a16 program counter (pc) stop clock reset idle power control register data bus sfr bus interface sfr_address sfr_control sfr_write_data sfr_read_data d8 d8 b register d8 d8 accumulator d8 d8 d8 d8 d8 d8 d8 d8 mem_write_data mem_read_data d8 sram address register sram (256 x 8) d8 stack pointer d8 rev. 1.0 81 c8051f360/1/2/3/4/5/6/7/8/9 figure 9.1. cip-51 block diagram 9.2. programming a nd debugging support a c2-based serial interface is provided for in-sys tem programming of the flash program memory and com - munication with on-chip debug support logic. the re -p rogrammable flash can also be read and changed by the application software using the movc and movx instructions. this featur e allows program memory to be used for non-volatile data storage as well as updating program code under software control. the on-chip debug support logic facilitates full speed in-circuit debugging, a llowing the setting of hardware breakpoints and watch points, starting, stopping and si ngle stepping through program execution (including interrupt service routines), examination of the program's call stack, and reading/wr iting the contents of reg - isters and memory. this method of on-chip debug is comp letely non-intrusive and non-invasive, requiring no ram, stack, timers, or other on-chip resources. the cip-51 is support ed by devel opment tools from silicon labs and third party vendors. silicon labs pro - vides an integrated development environment (ide) includ ing editor, macro assembler, debugger and pro - grammer. the ide's debugger and programmer interface to the cip-51 via its c2 interface to provide fast a nd efficient in-system device programming and deb ugging. third party macro assemblers and c compil - ers are also available. c8051f360/1/2/3/4/5/6/7/8/9 82 rev. 1.0 9.3. instruction set the instruction set of the cip-51 system controller is fully compatible with the standard mcs-51? instruc - tion set; standard 8051 development tools can be used to develop software for the cip-51. all cip-51 in structions are the binary and fu nctional equivalent of their mcs-51? counterparts, including opcodes, addressing modes and effect on psw flags. however, in struction timing is different than that of the stan - dard 8051. 9.3.1. instruction and cpu timing in many 8051 implementations, a distinction is ma de between machine cycles and clock cycles, with machine cycles varying from 2 to 12 clock cycles in length. however, the cip-51 implementation is based solely on clock cycle timing. all instructio n timings are specified in terms of clock cycles. due to the pipelined architecture of the cip-51, most in structions execute in the same number of clock cycles as there are program bytes in the instruction. conditional branch instruct ions take one less clock cycle to complete when the branch is not taken as opposed to when the branch is taken. table 9.1 is the cip-51 instruct ion set summary , which includes the mnemonic, number of bytes, and number of clock cycles for each instruction. 9.3.2. movx instruction and program memory in the cip-51, the movx instruction serves three pur poses: accessing on-chip xram, accessing off-chip xram, and accessing on-chip program flash memory. the flash access feature provides a mechanism for user software to update program code and use the program memory space for non-volatile data stor - age (see section ?13. flash memory? on page 135 ). the external memory interface provides a fast access to off-chip xram (or memory-mapped peripherals) via the movx instruction. refer to section ?15. external data memory interface and on-chip xram? on page 153 for details. table 9.1. cip-51 instruction set summary mnemonic description bytes clock cycles arithmetic operations add a, rn add register to a 1 1 add a, direct add direct byte to a 2 2 add a, @ri add indirect ram to a 1 2 add a, #data add immediate to a 2 2 addc a, rn add register to a with carry 1 1 addc a, direct add direct byte to a with carry 2 2 addc a, @ri add indirect ram to a with carry 1 2 addc a, #data add immediate to a with carry 2 2 subb a, rn subtract register from a with borrow 1 1 subb a, direct subtract direct byte from a with borrow 2 2 subb a, @ri subtract indirect ram from a with borrow 1 2 subb a, #data subtract immediate from a with borrow 2 2 inc a increment a 1 1 inc rn increment register 1 1 inc direct increment direct byte 2 2 inc @ri increment indirect ram 1 2 rev. 1.0 83 c8051f360/1/2/3/4/5/6/7/8/9 dec a decrement a 1 1 dec rn decrement register 1 1 dec direct decrement direct byte 2 2 dec @ri decrement indirect ram 1 2 inc dptr increment data pointer 1 1 mul ab multiply a and b 1 4 div ab divide a by b 1 8 da a decimal adjust a 1 1 logical operations anl a, rn and register to a 1 1 anl a, direct and direct byte to a 2 2 anl a, @ri and indirect ram to a 1 2 anl a, #data and immediate to a 2 2 anl direct, a and a to direct byte 2 2 anl direct, #data and immediate to direct byte 3 3 orl a, rn or register to a 1 1 orl a, direct or direct byte to a 2 2 orl a, @ri or indirect ram to a 1 2 orl a, #data or immediate to a 2 2 orl direct, a or a to direct byte 2 2 orl direct, #data or immediate to direct byte 3 3 xrl a, rn exclusive-or register to a 1 1 xrl a, direct exclusive-or direct byte to a 2 2 xrl a, @ri exclusive-or indirect ram to a 1 2 xrl a, #data exclusive-or immediate to a 2 2 xrl direct, a exclusive-or a to direct byte 2 2 xrl direct, #data exclusive-or immediate to direct byte 3 3 clr a clear a 1 1 cpl a complement a 1 1 rl a rotate a left 1 1 rlc a rotate a left through carry 1 1 rr a rotate a right 1 1 rrc a rotate a right through carry 1 1 swap a swap nibbles of a 1 1 data transfer mov a, rn move register to a 1 1 mov a, direct move direct byte to a 2 2 mov a, @ri move indirect ram to a 1 2 mov a, #data move immediate to a 2 2 mov rn, a move a to register 1 1 mov rn, direct move direct byte to register 2 2 mov rn, #data move immediate to register 2 2 mov direct, a move a to direct byte 2 2 mov direct, rn move register to direct byte 2 2 mov direct, direct move direct byte to direct byte 3 3 table 9.1. cip-51 instructi on set summary (continued) mnemonic description bytes clock cycles c8051f360/1/2/3/4/5/6/7/8/9 84 rev. 1.0 mov direct, @ri move indirect ram to direct byte 2 2 mov direct, #data move immediate to direct byte 3 3 mov @ri, a move a to indirect ram 1 2 mov @ri, direct move direct byte to indirect ram 2 2 mov @ri, #data move immediate to indirect ram 2 2 mov dptr, #data16 load dptr with 16-bit constant 3 3 movc a, @a+dptr move code byte relative dptr to a 1 3 movc a, @a+pc move code byte relative pc to a 1 3 movx a, @ri move external data (8-bit address) to a 1 3 movx @ri, a move a to external data (8-bit address) 1 3 movx a, @dptr move external data (16-bit address) to a 1 3 movx @dptr, a move a to external data (16-bit address) 1 3 push direct push direct byte onto stack 2 2 pop direct pop direct byte from stack 2 2 xch a, rn exchange register with a 1 1 xch a, direct exchange direct byte with a 2 2 xch a, @ri exchange indirect ram with a 1 2 xchd a, @ri exchange low nibble of indirect ram with a 1 2 boolean manipulation clr c clear carry 1 1 clr bit clear direct bit 2 2 setb c set carry 1 1 setb bit set direct bit 2 2 cpl c complement carry 1 1 cpl bit complement direct bit 2 2 anl c, bit and direct bit to carry 2 2 anl c, /bit and complement of direct bit to carry 2 2 orl c, bit or direct bit to carry 2 2 orl c, /bit or complement of direct bit to carry 2 2 mov c, bit move direct bit to carry 2 2 mov bit, c move carry to direct bit 2 2 jc rel jump if carry is set 2 2/3* jnc rel jump if carry is not set 2 2/3* jb bit, rel jump if direct bit is set 3 3/4* jnb bit, rel jump if direct bit is not set 3 3/4* jbc bit, rel jump if direct bit is set and clear bit 3 3/4* program branching acall addr11 absolute subroutine call 2 3* lcall addr16 long subroutine call 3 4* ret return from subroutine 1 5* reti return from interrupt 1 5* ajmp addr11 absolute jump 2 3* ljmp addr16 long jump 3 4* sjmp rel short jump (relative address) 2 3* jmp @a+dptr jump indirect relative to dptr 1 3* table 9.1. cip-51 instructi on set summary (continued) mnemonic description bytes clock cycles rev. 1.0 85 c8051f360/1/2/3/4/5/6/7/8/9 jz rel jump if a equals zero 2 2/3* jnz rel jump if a does not equal zero 2 2/3* cjne a, direct, rel compare direct byte to a and jump if not equal 3 3/4* cjne a, #data, rel compare immediate to a and jump if not equal 3 3/4* cjne rn, #data, rel compare immediate to register and jump if not eq ual 3 3/4* cjne @ri, #data, rel compare immediate to indirect and jump if not eq ual 3 4/5* djnz rn, rel decrement register and jump if not zero 2 2/3* djnz direct, rel decrement direct byte and jump if not zero 3 3/4* nop no operation 1 1 * branch instructions will incur a cache- miss penalty if the branch target location is not already stored in the branch target cache. see section ?14. branch target cache? on page 145 for more details. notes on registers, operands and addressing modes: rn - register r0-r7 of the currently selected register bank. @ri - data ram location addressed indirectly through r0 or r1. rel - 8-bit, signed (2s complement) offset relative to t he first byte of the followi ng instruction. used by sjmp and all conditional jumps. direct - 8-bit internal data location?s address. this could be a direct-access data ram location (0x00- 0x7f) or an sfr (0x80-0xff). #data - 8-bit constant #data16 - 16-bit constant bit - direct-accessed bit in data ram or sfr addr11 - 11-bit destination address used by acall and ajmp. the destination mu st be within the same 2k-byte page of program memory as the first byte of the following instruction. addr16 - 16-bit destination address used by lcall a nd ljmp. the destination may be anywhere within the 64k-byte program memory space. there is one unused opcode (0xa5) that performs the same function as nop. all mnemonics copyrighted ? intel corporation 1980. table 9.1. cip-51 instructi on set summary (continued) mnemonic description bytes clock cycles c8051f360/1/2/3/4/5/6/7/8/9 86 rev. 1.0 9.4. memory organization the memory organization of the cip-51 system controller is similar to that of a standard 8051. there are two separate memory spaces: program memory and data memory. program and data memory share the same address space but are accessed via different instruction types. there are 256 bytes of internal data m emory and 32k bytes (c8051f360/1/2/3/4/5/6/7) or 16k bytes (c8051f368/9) of internal program mem - ory address space implemented within the cip-51. t he cip-51 memory organization is shown in figure 9.2 . flash (in-system programmable in 1024 byte sectors) program memory 0x0000 (direct and indirect addressing) 0x00 0x7f upper 128 ram (indirect addressing only) 0x80 0xff special function register's (direct addressing only) reserved 0x7c00 0x7bff data memory general purpose registers 0x1f 0x20 0x2f bit addressable lower 128 ram (direct and indirect addressing) 0x30 c8051f360/1/2/3/4/5/6/7 flash (in-system programmable in 1024 byte sectors) 0x0000 0x4000 0x3fff c8051f368/9 external data address space internal data address space xram - 1024 bytes (accessable using movx instruction) 0x0000 0x03ff same 1024 bytes as from 0x0000 to 0x03ff, wrapped on 1024-byte boundaries 0x0400 0xffff reserved figure 9.2. memory map 9.4.1. program memory the cip-51 core has a 64 kb program memory space. the c8051f 36 0/1/2/3/4/5/6/7 implement 32 kb of this program memory space as in-system, re-programmable flash memory, orga nized in a contiguous block from addresses 0x0000 to 0x7bff. ad dresses above 0x7bff are reserved on the 32 kb devices. th e c8051f368/9 implement 16 kb of flash from addresses 0x0000 to 0x3fff. program memory is normally assumed to be read-only . however, the cip-51 can write to program memory by setting the program store write enable bit (psctl.0) and using the movx instru ction. this feature pro - vides a mechanism for the cip-51 to update program code and use the program memory space for non- volatile data storage. refer to section ?13. flash memory? on page 135 for further details. rev. 1.0 87 c8051f360/1/2/3/4/5/6/7/8/9 9.4.2. data memory the cip-51 implements 256 bytes of internal ram mapped into the data memory space from 0x00 through 0x ff. the lower 128 bytes of data memory are used for general purpose registers and memory. either d irect or indirect addressing may be used to access the lower 128 bytes of data memory. locations 0x00 thr ough 0x1f are addressable as four banks of gene ral purpose registers, each bank consisting of eight byte-wide registers. the next 16 bytes, locations 0x20 through 0x2f, ma y eithe r be addressed as bytes or as 128 bit locations accessible with the direct addressing mode. the upper 128 bytes of data memory are accessible only by i ndir ect addressing. this region occupies the same address space as the special function regist ers (sfr) but is physically separate from the sfr space. the addressing mode used by an instruction when accessing locations above 0x7f determines whether the cpu accesses the upper 128 bytes of data memory space or the sfr?s. instructions that use direc t addressing will access the sfr space. instructions using indirect addressing above 0x7f access the upper 128 bytes of data memory. figure 9.2 illustrates the data memory organization of the cip-51. 9.4.3. general purpose registers the lower 32 bytes of data memory, locations 0x00 through 0x1f, may be addressed as four banks of gen - eral-purpose registers. each bank consists of eigh t b yte-wide registers designated r0 through r7. only one of these banks may be enabled at a time. two bi ts in the program status word, rs0 (psw.3) and rs1 (psw.4), select the active register bank (see description of the psw in sfr definition 9.8 ). this allows fast context switching when entering subroutines and inte rrupt service routines. indirect addressing modes use registers r0 and r1 as index registers. 9.4.4. bit addressable locations in addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20 through 0x2f are also accessible as 128 individually addressable bits. each bit has a bit address from 0x 00 to 0x7f. bit 0 of the byte at 0x20 has bit address 0x00 while bit 7 of the byte at 0x20 has bit address 0 x07. bit 7 of the byte at 0x2f has bit address 0x7f. a bit access is distinguished from a full byte access by the type of instruction used (bit source or destinat ion operands as opposed to a byte source or destina - tion). the mcs-51? assembly language allows an alte rna te notation for bit addressing of the form xx.b where xx is the byte address and b is the bit position within the byte. for example, the instruction: mov c, 22.3h moves the boolean value at 0x13 (bit 3 of the byte at location 0x22) into the carry flag. 9.4.5. stack a programmer's stack can be located anywhere in the 256 byte data memory. the stack area is designated using the stack pointer (sp, addres s 0x81) sfr. the sp will point to the last location used. the next value pushed on the stack is placed at sp +1 and then sp is incremented. a re set initializes the stack pointer to location 0x07; therefore, the first value pushed on th e stack is placed at location 0x08, which is also the first register (r0) of register bank 1. thus, if more than one register bank is to be used, the sp should be initialized to a location in the data memory not being used for data storage. the stack depth can extend up to 256 bytes. the mcus also have built-in hardware for a stack record which is accessed by the debug logic. the stack r ecord is a 32-bit shift register, where each push or increment sp pushes one record bit onto the register, c8051f360/1/2/3/4/5/6/7/8/9 88 rev. 1.0 and each call pushes two record bits onto the regist er. (a pop or decrement sp pops one record bit, and a ret pops two record bits, also.) the stack record circuitry can also detect an overflow or underflow on the 32-bit shift register, and can notify the d ebug software even with the mcu running at speed. 9.4.6. special function registers the direct-access data memory locations from 0x80 to 0xff constitute the sp ecial function registers (sfr?s). the sfr?s provide control and data exchange with the cip-51's resources and peripherals. the cip-51 duplicates the sfr?s found in a typical 8051 implementation as well as implementing additional sfr?s used to configure and access the sub-systems uni que to the mcu. this allows the addition of new functionality while retaining compatibi lity with the mcs-51? instruction set. ta b l e 9.2 lis ts the sfr?s imple - mented in the cip-51 system controller. the sfr registers are accessed whenever the direct addressing mode is used to access memory loca - tions from 0x80 to 0xff. sfr?s with addresses ending in 0x0 or 0x 8 (e.g. p0, tcon, p1, scon, ie, etc.) are bit-addressable as well as byte-addressable. all other sfr?s are byte-addressable only. unoccupied addresses in the sfr space are reserved for future use. accessing t hese areas will have an indeterminate effect and should be avoided. refer to the corres ponding pages of the data sheet, as indicated in ta b l e 9.3 , for a detailed description of each register. 9.4.6.1. sfr paging the cip-51 features sfr p aging, allowing the device to map many sfr?s into the 0x80 to 0xff memory address space. the sfr memory space has 256 pages . in this way, each memory location from 0x80 to 0xff can access up to 256 sfr?s. the c8051f36x fam ily of devices utilizes two sfr pages: 0 and f. sfr pages are selected using the special function register page selection register, sfrpage (see sfr def - inition 9.2 ). the procedure for reading and writing an sfr is as follows: 1. select the appropriate sfr page number using the sfrpage register. 2. use direct accessing mode to read or write t h e special function register (mov instruction). 9.4.6.2. interrupts and sfr paging when an interrupt occu rs , the sfr page register w ill automatically switch to sf r page 0, where all regis - ters containing the interrupt flag bits are accessible. th e automatic sfr page switch function conveniently removes the burden of switching sfr pages from the inte rrupt service routine. upon execution of the reti instruction, the sfr page is automa tically restored to the sfr page in use prior to the interrupt. this is accomplished via a three-byte sfr page stack . the top byte of the stack is sfrpage, the current sfr page. the second byte of the sfr page stack is sfrnext. the third, or bottom byte of the sfr page stack is sfrlast. on inte rrupt, the current sfrpage value is pushed to the sfrnext byte, and the value of sfrnext is pushed to sfrlast. hardware then loads sfrp age with the sfr page containing the flag bit associated with the interr upt. on a return from interrupt, the sfr page stack is popped result - ing in the value of sfrnext returning to the sfrpage register, thereby restoring the sfr page context without s oftware intervention. the valu e in sfrlast (0x00 if there is no sfr page value in the bottom of the stack) of the stack is placed in sfrnext regist er. if desired, the values stored in sfrnext and sfr - last may be modified during an interrupt, enabling the cpu to return to a different sfr page upon exe - cution of the reti instruction (on in te rrupt exit). modifying registers in the sfr page stack does not cause a push or pop of the st ack. only interrupt calls and returns will cause push/ pop operations on the sfr page stack. sfrnext sfrpage sfrlast cip-51 interrupt logic sfrpgcn bit rev. 1.0 89 c8051f360/1/2/3/4/5/6/7/8/9 figure 9.3. sfr page stack automatic hardware switching of the sfr page on interrupts may be enabled or disabled as desired using the sfr automatic page control enab le bit located in the sfr page control register (sfr0cn). this function defaults to ?enabled? upon reset. in this way, th e autoswitching function will be enabled unless dis - abled in software. a summary of the sfr locations (address and sfr page) is provided in table 9.2. in the form of an sfr memory map. each memory location in the map has an sfr page row, denoting the page in which that sfr resid es. note that certain sfr?s are accessible from all sfr pages, and are denoted by the back - ground shading in the table. for example, the port i/o r egisters p0, p1, p2, and p3 all have a shaded background, indicating these sfr?s are accessible from all sfr pages regardless of the sfrpage regis - ter value. c8051f360/1/2/3/4/5/6/7/8/9 90 rev. 1.0 9.4.6.3. sfr page stack example the following is an example that shows the operation of the sfr page stack during interrupts. in this example, the sfr page control is left in the default enabled state (i.e., sfrpgen = 1), and the cip-51 is executing in-line c ode that is writing values to oscicn (sfr ?oscicn?, located at address 0xb6 on sfr page 0x0f). the device is also usin g the programmable counter array (pca) and the 10-bit adc (adc0) window comparator to monitor a voltage. the pca is timing a critical control function in its interrupt service routine (i sr), so its interrupt is enabled and is set to high priority. the adc0 is monitoring a voltage that is less important, but to minimize the software overhead its window comparator is being used with an associated isr that is set to low priority. at this point, the sfr page is set to access the oscicn sfr (sfrpage = 0x0f). see figure 9.4 below. 0x0f (oscicn) sfrpage sfrlast sfrnext sfr page stack sfr's figure 9.4. sfr page stack while us ing sfr page 0x0f to access oscicn while cip-51 executes in-line code (writing values to oscicn in this example), adc0 window compara - tor interrupt occurs. the cip-51 vectors to the adc0 window comparator isr and pushes the current sfr page value (sfr page 0x0f) in to sfrnext in the sfr page s ta ck. sfr page 0x00 is then auto - matically placed in the sfrpage register. sfrpage is co nsidered the ?top? of the sfr page stack. soft - ware can now access the adc0 sfr?s. sof tware may switch to any sf r page by writing a new value to the sfrpage register at any time during the adc0 is r to access sfr?s that are not on sfr page 0x00. see figure 9.5 below. 0x00 (adc0) 0x0f (oscicn) sfrpage sfrlast sfrnext sfrpage pushed to sfrnext sfr page 0x00 automatically pushed on stack in sfrpage on adc0 interrupt rev. 1.0 91 c8051f360/1/2/3/4/5/6/7/8/9 figure 9.5. sfr page stack after adc 0 window comparator interrupt occurs while in the adc0 isr, a pca interrupt occurs . recall the pca interrupt is configured as a high priority interrupt, while the adc0 inte rrupt is configured as a low priority interrupt. thus , the cip-51 will now vector to the high priority pca isr. upon doing so, the cip-51 will automatically place sfr page 0x00 into the sfrpage register. the value that was in the sfrpage register before the pca in terrupt (sfr page 0x00 for adc0) is pushed down the sta ck into sfrnext. likewise, the value that was in the sfrnext register before the pca interrupt (in this case sfr page 0x 0f for oscicn) is pushed down to the sfrlast reg - ister, the ?bottom? of the stack. note that a value stored in sfrlast (via a previous software write to the sfrlast register) will be overwritten. see figure 9.6 below. 0x00 (pca) 0x00 (adc0) 0x0f (oscicn) sfrpage sfrlast sfrnext sfr page 0x00 automatically pushed on stack in sfrpage on pca interrupt sfrpage pushed to sfrnext sfrnext pushed to sfrlast figure 9.6. sfr page stac k upon pca interrupt occu rring during an adc0 isr c8051f360/1/2/3/4/5/6/7/8/9 92 rev. 1.0 on exit from the pca interrupt se rvice routine, the cip-51 will return to the adc0 window comparator isr. on execution of the reti inst ruction, sfr page 0x00 used to access the pca registers will be auto - matically popped off of the sfr page s tack, and the contents of the sfrnext register will be moved to the sfrpage register. software in the adc0 isr can continue to access sfr?s as it did prior to the pca interrupt. likewise, the contents of sfrlast are mo ved to the sfrnext register. recall this was the sfr page value 0x0f being used to access os cicn before the adc0 interrupt occurred. see figure 9.7 below. 0x00 (adc0) 0x0f (oscicn) sfrpage sfrlast sfrnext sfr page 0x00 automatically popped off of the stack on return from interrupt sfrnext popped to sfrpage sfrlast popped to sfrnext figure 9.7. sfr page stack u pon return from pca interrupt rev. 1.0 93 c8051f360/1/2/3/4/5/6/7/8/9 on the execution of the reti instruction in the adc0 window comparator isr, the value in sfrpage register is overwritten with the contents of sfrne xt. the cip-51 may now access the oscicn sfr bits as it did prior to the interrupts occurring. see figure 9.8 below. 0x0f (oscicn) sfrpage sfrlast sfrnext sfr page 0x00 automatically popped off of the stack on return from interrupt sfrnext popped to sfrpage figure 9.8. sfr page stack upon re turn from adc2 window interrupt note that in the above example, all three bytes in the sfr page stack are accessible via the sfrpage, sfrnext, and sfrlast special function registers. if the stack is altered wh ile servicing an in terrupt, it is possible to return to a different sfr page upon interrup t exit than selected prior to the interrupt call. direct access to the sfr page stack can be useful to enable real-time operating systems to control and manage context switching between multiple tasks. push operations on the sfr page stack only occur on inter rupt service, and pop operations only occur on interrupt exit (execution on the reti instruction). the automatic switching of the sfrpage and operation of the sfr page stack as described above can be disabled in software by clearing the sfr automatic page enable bit (sfrpgen) in the sfr page control register (sfr0cn). see sfr definition 9.1 . c8051f360/1/2/3/4/5/6/7/8/9 94 rev. 1.0 sfr definition 9.1. sfr0cn: sfr page control bits 7?1: reserved. read = 0000 000b. must write 0000000b. bit 0: sfrpgen: sfr automatic page control enable. upon interrupt, the c8051 core will vector to the specified in terrupt service routine and auto- matically switch to sfr page 0. this bit is used to control this autopaging function. 0: sfr automatic paging disabled. c8051 co re will not automatically change to sfr page 0. 1: sfr automatic paging enabl ed. upon interr upt, the c8051 will automatically switch to sfr page 0. sfr page: sfr address: f 0xe5 r/w r/w r/w r/w r/w r/w r/w r/w reset value reserved reserved reserved reserved reserved reserved reserved sfrpgen 00000001 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr definition 9.2. sfrpage: sfr page bits 7?0: sfr page bits: byte represents the sf r page the c8051 mcu uses when reading or mod- ifying sfr?s. write: sets the sfr page. read: byte is the sfr page the c8051 mcu is using. when enabled in the sfr page control register (sfr0cn), the c8051 will automatically switch to sfr page 0x00 and return to the previous sfr page upon return from interrupt (unless sfr stack was altered before a returning from the interrupt). sfrpage is the top byte of the sfr page stack, and push/pop events of this stack are caused by interrupts (and not by reading/writing to the sfrpage register) sfr page: sfr address: all pages 0xa7 r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rev. 1.0 95 c8051f360/1/2/3/4/5/6/7/8/9 sfr definition 9.3. sfrnext: sfr next register bits 7?0: sfr page stack bits: sfr page context is retained upon interrupts/return from interrupts in a 3 byte sfr page stack: sfrpage is the fi rst entry, sfrnext is the second, and sfr- last is the third entry. the sfr stack bytes ma y be used alter the context in the sfr page stack, and will not cause the stack to ?push? or ?pop?. only interrupts and return from inter- rupts cause pushes and pops of the sfr page stack. write: sets the sfr page contained in the se cond byte of the sfr stack. this will cause the sfrpage sfr to have this sfr page value upon a return from interrupt. read: returns the value of the sfr page contai ned in the second byte of the sfr stack. this is the value that will go to the sfr pa ge register upon a re turn from interrupt. sfr page: sfr address: all pages 0x85 r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr definition 9.4. sfrlast: sfr last register bits 7?0: sfr page stack bits: sfr page context is retained upon interrupts/return from interrupts in a 3 byte sfr page stack: sfrpage is the fi rst entry, sfrnext is the second, and sfr- last is the third entry. the sfr stack bytes ma y be used alter the context in the sfr page stack, and will not cause the stack to ?push? or ?pop?. only interrupts and return from inter- rupts cause pushes and pops of the sfr page stack. write: sets the sfr page in the last entry of the sfr stack. this will cause the sfrnext sfr to have this sfr page value upon a return from interrupt. read: returns the value of the sfr page contained in the last entry of the sfr stack. sfr page: sfr address: all pages 0x86 r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 c8051f360/1/2/3/4/5/6/7/8/9 96 rev. 1.0 table 9.2. special function re gister (sfr) memory map address sfr page 0(8) 1(9) 2(a) 3(b) 4(c) 5(d) 6(e) 7(f) f8 0 f spi0cn pca0l pca0h pca0cpl0 pca0cph0 pca0cpl4 pca0cph4 vdm0cn f0 0 f bmac0bl p0mdin mac0bh p1mdin p0mat p2mdin p0mask p3mdin pca0cpl5 pca0cph5 - emi0tc e8 0 f adc0cn pca0cpl1 pca0cph1 pca0cpl2 pca0cph2 pca0cpl3 pca0cph3 rstsrc e0 0 f acc p1mat xbr0 p1mask xbr1 - - it01cf - sfr0cn eie1 eie2 d8 0 f pca0cn pca0md pca0cpm0 pca0cpm1 pca0cpm2 pca0cpm3 pca0cpm4 pca0cpm5 d0 0 f psw ref0cn mac0acc0 cch0lc mac0acc1 cch0ma mac0acc2 p0skip mac0acc3 p1skip mac0ovr p2skip mac0cf p3skip c8 0 f tmr2cn - cch0tn tmr2rll tmr2rlh tmr2l tmr2h - eip1 mac0sta eip2 c0 0 f smb0cn smb0cf smb0dat adc0gtl adc0gth adc0ltl adc0lth - emi0cf b8 0 f ip ida0cn amx0n amx0p adc0cf adc0l adc0h - oscicl b0 0 f p3 p2mat pll0mul p2mask pll0flt - pll0cn - - p4 flscl oscxcn flkey oscicn a8 0 f ie - pll0div emi0cn - - - flstat - osclcn mac0rndl p4mdout mac0rndh p3mdout a0 0 f p2 spi0cfg spi0ckr spi0dat mac0al p0mdout mac0ah p1mdout - p2mdout sfrpage 98 0 f scon0 sbuf0 cpt1cn cpt0cn cpt1md cpt0md cpt1mx cpt0mx 90 0 f p1 tmr3cn tmr3rll tmr3rlh tmr3l tmr3h ida0l ida0h 88 0 f tcon tmod tl0 tl1 th0 th1 ckcon psctl clksel 80 0 f p0 sp dpl dph - cch0cn sfrnext sfrlast pcon 0(8) 1(9) 2(a) 3(b) 4(c) 5(d) 6(e) 7(f) bit-addressable shaded sfrs are accessible on all sfr pages regardless of the contents of sfrpage rev. 1.0 97 c8051f360/1/2/3/4/5/6/7/8/9 table 9.3. special function registers sfrs are listed in alphabetical order. all undefined sfr locations are reserved. register address sfr page description page no. acc 0xe0 all pages accumulator page 104 adc0cf 0xbc all pages adc0 configuration page 56 1 adc0cn 0xe8 all pages adc0 control page 57 1 adc0gth 0xc4 all pages adc0 greater-than high byte page 58 1 adc0gtl 0xc3 all pages adc0 greater-than low byte page 58 1 adc0h 0xbe all pages adc0 data word high byte page 56 1 adc0l 0xbd all pages adc0 data word low byte page 56 1 adc0lth 0xc6 all pages adc0 less-than high byte page 59 1 adc0ltl 0xc5 all pages adc0 less-than low byte page 59 1 amx0n 0xba all pages amux0 negative channel select page 55 1 amx0p 0xbb all pages amux0 positive channel select page 54 1 b 0xf0 all pages b register page 104 cch0cn 0x84 f cache control page 149 cch0lc 0xd2 f cache lock page 151 cch0ma 0xd3 f cache miss accumulator page 152 cch0tn 0xc9 f cache tuning page 150 ckcon 0x8e all pages clock control page 254 clksel 0x8f f system clock select page 174 cpt0cn 0x9b all pages comparator0 control page 73 cpt0md 0x9d all pages comparator0 configuration page 75 cpt0mx 0x9f all pages comparator0 mux selection page 74 cpt1cn 0x9a all pages comparator1 control page 76 cpt1md 0x9c all pages comparator1 configuration page 78 cpt1mx 0x9e all pages comparator1 mux selection page 77 dph 0x83 all pages data pointer high byte page 102 dpl 0x82 all pages data pointer low byte page 102 eie1 0xe6 all pages extended interrupt enable 1 page 112 eie2 0xe7 all pages extended interrupt enable 2 page 114 eip1 0xce f extended interrupt priority 1 page 113 eip2 0xcf f extended interrupt priority 2 page 114 notes: 1. ref ers to a register in the c8051f360/1/2/6/7/8/9 only. 2. r efers to a register in the c8051f360/3 only. c8051f360/1/2/3/4/5/6/7/8/9 98 rev. 1.0 emi0cf 0xc7 f emif configuration page 156 2 emi0cn 0xaa all pages emif control page 155 2 emi0tc 0xf7 f emif timing control page 161 2 flkey 0xb7 0 flash lock and key page 142 flscl 0xb6 0 flash scale page 143 flstat 0xac f flash status page 152 ida0cn 0xb9 all pages idac0 control page 65 1 ida0h 0x97 all pages idac0 high byte page 65 1 ida0l 0x96 all pages idac0 low byte page 66 1 ie 0xa8 all pages interrupt enable page 110 ip 0xb8 all pages interrupt priority page 111 it01cf 0xe4 all pages int0/int1 configuration page 116 mac0acc0 0xd2 0 mac0 accumulator byte 0 (lsb) page 126 mac0acc1 0xd3 0 mac0 accumulator byte 1 page 125 mac0acc2 0xd4 0 mac0 accumulator byte 2 page 125 mac0acc3 0xd5 0 mac0 accumulator byte 3 (msb) page 125 mac0ah 0xa5 0 mac0 a register high byte page 123 mac0al 0xa4 0 mac0 a register low byte page 124 mac0bh 0xf2 0 mac0 b register high byte page 124 mac0bl 0xf1 0 mac0 b register low byte page 124 mac0cf 0xd7 0 mac0 configuration page 122 mac0ovr 0xd6 0 mac0 accumulator overflow page 126 mac0rndh 0xaf 0 mac0 rounding register high byte page 126 mac0rndl 0xae 0 mac0 rounding register low byte page 127 mac0sta 0xcf 0 mac0 status register page 123 oscicl 0xbf f internal oscillator calibration page 170 oscicn 0xb7 f internal oscillator control page 171 osclcn 0xad f internal l-f o scillator control page 172 oscxcn 0xb6 f external oscillator control page 175 p0 0x80 all pages port 0 latch page 190 p0mask 0xf4 0 port 0 mask page 192 table 9.3. special func tion registers (continued) sfrs are listed in alphabetical order. all undefined sfr locations are reserved. register address sfr page description page no. notes: 1. refers to a register in the c8051f360/1/2/6/7/8/9 only. 2. refers to a register in the c8051f360/3 only. rev. 1.0 99 c8051f360/1/2/3/4/5/6/7/8/9 p0mat 0xf3 0 port 0 match page 192 p0mdin 0xf1 f port 0 input mode page 191 p0mdout 0xa4 f port 0 output mode configuration page 191 p0skip 0xd4 f port 0 skip page 192 p1 0x90 all pages port 1 latch page 193 p1mask 0xe2 0 port 1 mask page 195 p1mat 0xe1 0 port 1 match page 194 p1mdin 0xf2 f port 1 input mode page 193 p1mdout 0xa5 f port 1 output mode configuration page 194 p1skip 0xd5 f port 1 skip page 194 p2 0xa0 all pages port 2 latch page 195 p2mask 0xb2 0 port 2 mask page 197 p2mat 0xb1 0 port 2 match page 197 p2mdin 0xf3 f port 2 input mode page 196 p2mdout 0xa6 f port 2 output mode configuration page 196 p2skip 0xd6 f port 2 skip page 197 p3 0xb0 all pages port 3 latch page 198 p3mdin 0xf4 f port 3 input mode page 198 p3mdout 0xaf f port 3 output mode configuration page 199 p3skip 0xd7 f port 3 skip page 199 p4 0xb5 all pages port 4 latch page 200 p4mdout 0xae f port 4 output mode configuration page 200 pca0cn 0xd8 all pages pca control page 276 pca0cph0 0xfc all pages pca module 0 capture/compare high byte page 280 pca0cph1 0xea all pages pca module 1 capture/compare high byte page 280 pca0cph2 0xec all pages pca module 2 capture/compare high byte page 280 pca0cph3 0xee all pages pca module 3 capture/compare high byte page 280 pca0cph4 0xfe all pages pca module 4 capture/compare high byte page 280 pca0cph5 0xf6 all pages pca module 5 capture/compare high byte page 280 pca0cpl0 0xfb all pages pca module 0 capture/compare low byte page 279 pca0cpl1 0xe9 all pages pca module 1 capture/compare low byte page 279 table 9.3. special func tion registers (continued) sfrs are listed in alphabetical order. all undefined sfr locations are reserved. register address sfr page description page no. notes: 1. refers to a register in the c8051f360/1/2/6/7/8/9 only. 2. refers to a register in the c8051f360/3 only. c8051f360/1/2/3/4/5/6/7/8/9 100 rev. 1.0 pca0cpl2 0xeb all pages pca module 2 capture/compare low byte page 279 pca0cpl3 0xed all pages pca module 3 capture/compare low byte page 279 pca0cpl4 0xfd all pages pca module 4 capture/compare low byte page 279 pca0cpl5 0xf5 all pages pca module 5 capture/compare low byte page 279 pca0cpm0 0xda all pages pca module 0 mode page 278 pca0cpm1 0xdb all pages pca module 1 mode page 278 pca0cpm2 0xdc all pages pca module 2 mode page 278 pca0cpm3 0xdd all pages pca module 3 mode page 278 pca0cpm4 0xde all pages pca module 4 mode page 278 pca0cpm5 0xdf all pages pca module 5 mode page 278 pca0h 0xfa all pages pca counter high byte page 279 pca0l 0xf9 all pages pca counter low byte page 279 pca0md 0xd9 all pages pca mode page 277 pcon 0x87 all pages power control page 106 pll0cn 0xb3 f pll control page 180 pll0div 0xa9 f pll divider page 180 pll0flt 0xb2 f pll filter page 181 pll0mul 0xb1 f pll multiplier page 181 psctl 0x8f 0 flash write/erase control page 142 psw 0xd0 all pages program status word page 103 ref0cn 0xd1 all pages voltage reference control page 68 1 rstsrc 0xef all pages reset source page 133 sbuf0 0x99 all pages uart 0 data buffer page 226 scon0 0x98 all pages uart 0 control page 225 sfr0cn 0xe5 f sfr page control page 94 sfrlast 0x86 all pages sfr stack last page page 95 sfrnext 0x85 all pages sfr stack next page page 95 sfrpage 0xa7 all pages sfr page select page 94 smb0cf 0xc1 all pages smbus configuration page 208 smb0cn 0xc0 all pages smbus control page 210 smb0dat 0xc2 all pages smbus data page 212 table 9.3. special func tion registers (continued) sfrs are listed in alphabetical order. all undefined sfr locations are reserved. register address sfr page description page no. notes: 1. refers to a register in the c8051f360/1/2/6/7/8/9 only. 2. refers to a register in the c8051f360/3 only. rev. 1.0 101 c8051f360/1/2/3/4/5/6/7/8/9 sp 0x81 all pages stack pointer page 102 spi0cfg 0xa1 all pages spi configuration page 241 spi0ckr 0xa2 all pages spi clock ra te cont rol page 243 spi0cn 0xf8 all pages spi control page 242 spi0dat 0xa3 all pages spi data page 243 tcon 0x88 all pages timer/counter control page 252 th0 0x8c all pages timer/counter 0 high byte page 255 th1 0x8d all pages timer/counter 1 high byte page 255 tl0 0x8a all pages timer/counter 0 low byte page 255 tl1 0x8b all pages timer/counter 1 low byte page 255 tmod 0x89 all pages timer/counter mode page 253 tmr2cn 0xc8 all pages timer/counter 2 control page 258 tmr2h 0xcd all pages timer/counter 2 high byte page 259 tmr2l 0xcc all pages timer/counter 2 low byte page 259 tmr2rlh 0xcb all pages timer 2 reload register high byte page 259 tmr2rll 0xca all pages timer 2 reload register low byte page 259 tmr3cn 0x91 all pages timer 3 control page 262 tmr3h 0x95 all pages timer 3 high byte page 263 tmr3l 0x94 all pages timer 3 low byte page 263 tmr3rlh 0x93 all pages timer 3 reload register high byte page 263 tmr3rll 0x92 all pages timer 3 reload register low byte page 263 vdm0cn 0xff all pages v dd monitor control page 131 xbr0 0xe1 f port i/o crossbar control 0 page 188 xbr1 0xe2 f port i/o crossbar control 1 page 189 table 9.3. special func tion registers (continued) sfrs are listed in alphabetical order. all undefined sfr locations are reserved. register address sfr page description page no. notes: 1. refers to a register in the c8051f360/1/2/6/7/8/9 only. 2. refers to a register in the c8051f360/3 only. c8051f360/1/2/3/4/5/6/7/8/9 102 rev. 1.0 9.4.7. register descriptions following are descriptions of sfrs related to the operati on of the cip-51 system controller. reserved bits should not be set to logic ?1?. future product versions may use these bits to implement new features in which case the reset value of the bi t will be logic ?0?, selecting the feat ure's default state. detailed descrip - tions of the remaining sfrs are included in the se ctio ns of the data sheet associated with their corre - sponding system function. sfr definition 9.5. sp: stack pointer bits 7?0: sp: stack pointer. the stack pointer holds the location of the top of the stack. the stack pointer is incremented before every push operation. the sp r egister defaults to 0x07 after reset. sfr page: sfr address: all pages 0x81 r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr definition 9.6. dpl: data pointer low byte bits 7?0: dpl: data pointer low. the dpl register is the low byte of the 16-b it dptr. dptr is used to access indirectly addressed xram and flash memory. sfr page sfr address: all pages 0x82 r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr definition 9.7. dph: data pointer high byte bits 7?0: dph: data pointer high. the dph register is the high byte of the 16-b it dptr. dptr is used to access indirectly addressed xram and flash memory. sfr page: sfr address: all pages 0x83 r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rev. 1.0 103 c8051f360/1/2/3/4/5/6/7/8/9 sfr definition 9.8. psw: program status word bit 7: cy: carry flag. this bit is set when the last arithmetic operat ion resulted in a carry (addition) or a borrow (subtraction). it is cleared to 0 by all other arithmetic operations. bit 6: ac: auxiliary carry flag this bit is set when the last arithmetic operati on resulted in a carry into (addition) or a borrow from (subtraction) the high order nibble. it is cleared to 0 by all other arithmetic operations. bit 5: f0: user flag 0. this is a bit-addressable, general purpose flag for use under software control. bits 4?3: rs1?rs0: register bank select. these bits select which register ban k is used during register accesses. bit 2: ov: overflow flag. this bit is set to 1 under the following circumstances: ? an add, addc, or subb instructi on causes a sign-change overflow. ? a mul instruction results in an overflow (result is greater than 255). ? a div instruction causes a divide-by-zero condition. the ov bit is cleared to 0 by the add, addc, subb, mul, and div inst ructions in all other cases. bit 1: f1: user flag 1. this is a bit-addressable, general purpose flag for use under software control. bit 0: parity: parity flag. this bit is set to 1 if the sum of the eight bits in the accumulator is odd and cleared if the sum is even. sfr page: sfr address: all pages 0xd0 (bit addressable) r/wr/wr/wr/wr/wr/wr/w rreset value cy ac f0 rs1 rs0 ov f1 parity 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rs1 rs0 register bank address 0 0 0 0x00?0x07 0 1 1 0x08?0x0f 1 0 2 0x10?0x17 1 1 3 0x18?0x1f c8051f360/1/2/3/4/5/6/7/8/9 104 rev. 1.0 sfr definition 9.9. acc: accumulator bits 7?0: acc: accumulator. this register is the accumulator for arithmetic operations. sfr page: sfr address: all pages 0xe0 (bit addressable) r/w r/w r/w r/w r/w r/w r/w r/w reset value acc.7 acc.6 acc.5 acc.4 acc.3 acc.2 acc.1 acc.0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr definition 9.10. b: b register bits 7?0: b: b register. this register serves as a second accumu lator for certain arithmetic operations. sfr page: sfr address: all pages 0xf0 (bit addressable) r/w r/w r/w r/w r/w r/w r/w r/w reset value b.7 b.6 b.5 b.4 b.3 b.2 b.1 b.0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 9.5. power management modes the cip-51 core has two software programmable power management modes: idle and stop. idle mode halts the cpu while leaving the extern al peripherals and internal clocks active. in stop mode, the cpu is halted, all interrupts and timers (except the missing clock detector) are inactive, and the system clock is stopped. since clocks are running in idle mode, powe r consumption is dependent upon the system clock frequency and the number of peripherals left in active mode before entering idle. stop mode consumes the least power. sfr definition 9.11 describes the power cont rol regis ter (pcon) us ed to control the cip- 51's power management modes. although the cip-51 has idle and stop modes built in ( as with any standard 8051 architecture), power management of the entire mcu is better accomplished by enabling/disabling individual peripherals as needed. each analog peripheral can be disabled when not in use and put into low power mode. digital peripherals, such as timers or serial buses, draw littl e power whenever they are not in use. turning off the flash memory saves power, similar to entering idle mode. turning off the oscillator saves even more power, but requires a reset to restart the mcu. the c8051f36x devices feature an additional low-power suspend mode, which stop s the internal oscil - lator until an awakening event occurs. see section ?16.1.1. internal oscillator suspend mode? on page 170 for more information. rev. 1.0 105 c8051f360/1/2/3/4/5/6/7/8/9 9.5.1. idle mode setting the idle mode select bit (pcon.0) causes the cip-51 to halt the cpu and enter idle mode as soon as the instruction that sets the bit completes. all internal registers and memory maintain their original data. all analog and digital peripherals can remain active during idle mode. idle mode is terminated when an enabled interrupt or rst is asserted. the assertion of an enabled inter - rupt will cause the idle m ode selec tion bit (pcon.0) to be cleared and the cpu to resume operation. the pending interrupt will be serviced and the next instru ction to be executed after the return from interrupt (reti) will be the instruction immediat ely following the one that set the idle mode select bit. if idle mode is terminated by an internal or external reset, the cip-51 performs a normal reset sequence and begins pro - gram execution at address 0x0000. if enabled, the wdt will eventually cause an internal watc hdog reset and thereby terminate the idle mode. this feature protects the system from an unintended permanent shutdown in the event of an inadvertent write to the pcon register. if this behavior is not desired, the wdt may be disabled by software prior to entering the idle mode if the wdt was initially configured to allow this operation. this provides the oppor - tunity for additional power savings, allowing the system to remain in the idle mode indefinitely, waiting for an external stimulus to wake up the system. refer to section 22.3 for more information on the use and configuration of the wdt. note: any instruction which set s the idle bit should be immediately followed by an instruction which has two or more opcode bytes. for example: // in ?c?: pcon |= 0x01; // set idle bit pcon = pcon; // ... followed by a 3-cycle dummy instruction ; in assembly: orl pcon, #01h ; set idle bit mov pcon, pcon ; ... followed by a 3-cycle dummy instruction if the instruction following the write to the idle bit is a single-byte in struction and an interrupt occurs during the execution of the instruction of th e instruction which sets the idle bit, the cpu may not wake from idle mode when a future interrupt occurs. 9.5.2. stop mode setting the stop mode select bit (pcon.1) causes the ci p-51 to enter stop mode as soon as the instruc - tion that sets the bit completes. in stop mode, the cpu and oscillators are stopped, effectively shutting down all digital peripherals. each analog peripheral must be shut down individually prior to entering stop mode. stop mode can only be terminated by an internal or external reset. on re set, the cip-51 performs the normal reset sequence and begins program execution at address 0x0000. if enabled, the missing clock detect or will cause an internal reset and ther eby terminate th e stop mode. the missing clock detector should be disabled if the cpu is to be put to sleep for longer than the mcd timeout of 100 s. 9.5.3. suspend mode the c8051f36x device s feature a low-power suspend mode, which stops the internal oscillator until an awakening event occurs. see section ?16.1.1. internal oscillator su spend mode? on page 170 . c8051f360/1/2/3/4/5/6/7/8/9 106 rev. 1.0 sfr definition 9.11. pcon: power control bits 7?3: reserved. read = 0 00000b. must wr ite 000000b. bit 1: stop: stop mode select. writing a ?1? to this bit will place the cip-51 into stop mode. this bit will always read ?0?. 1: cip-51 forced into power-down mode. (t urns off oscillator). bit 0: idle: idle mode select. writing a ?1? to this bit will place the cip-51 into idle mode. this bit will always read ?0?. 1: cip-51 forced into idle mode. (shuts off cl ock to cpu, but clock to timers, interrupts, and all peripherals remain active.) sfr page: sfr address: all pages 0x87 r/w r/w r/w r/w r/w r/w r/w r/w reset value reserved reserved reserved reserved reserved reserved stop idle 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rev. 1.0 107 c8051f360/1/2/3/4/5/6/7/8/9 10. interrupt handler the c8051f36x family includes an extended interrup t system supporting a total of 16 interrupt sources with two priority levels. the allocati on of interrupt sources between on-chip peripherals and external input pins varies according to the specific version of the device. each interrupt source has one or more associ - ated interrupt-pending flag(s) located in an sfr. when a p eripheral or external source meets a valid inter - rupt condition, the associated interrupt -pending flag is set to logic ?1?. if interrupts are enabled for the source, an interrupt req uest is generated when the interrupt-pending flag is set. as soon as execution of the current instructio n is complete, the cpu generates an lcall to a prede - termined address to begin execution of an interrupt se rvice ro utine (isr). each isr must end with an reti instruction, which returns program execution to the next instruction that would have been executed if the interrupt request had not occurred. if interrupts are not enabled, the interrupt-pending flag is ignored by the hardware and program execution continues as normal. (the interrupt-pending flag is set to logic ?1? regard - less of the interrupt's enable/disable state.) each interrupt source can be individually enabled or di sabled through the use of an associated interrupt enable bit in the interrupt enable and extended interrupt enable sfrs. however, interrupts must first be globally enabled by setting the ea bit (ie.7) to logic ?1? before the individual interrupt enables are recog - nized. setting the ea bit to logic ?0? disables all in terrupt sources re gardless of the individual interrupt- enable settings. note that interrupts which occur when the ea bit is set to logic ?0? will be held in a pending state, and will not be serviced until the ea bit is set back to logic ?1?. note : an y instruction that clears a bit to disable an interrupt should be immediately followed by an instruc - tion that has two or more opcode bytes. usi ng ea (gl obal interrupt enable) as an example: // in 'c': ea = 0; // clear ea bit. ea = 0; // this is a dummy instruction with two-byte opcode. ; in assembly: clr ea ; clear ea bit. clr ea ; this is a dummy instruction with two-byte opcode. for example, if an interrupt is posted during the exec ution phase of a "clr ea" opcode (or any instruction which clears a bit to disable an interrupt source), an d the instruction is followed by a single-cycle instruc - tion, the interrupt may be taken. however, a read of the enable bit will return a '0' inside the interrupt ser - vice routine. when the bit-clearing op code is followed by a multi-cycle in struction, the interrupt will not be taken. some interrupt-pending flags are automatically cleare d by the hardware when the cpu vectors to the isr. however, most are not cleared by the hardware and must be cleared by software before returning from the isr. if an interrupt-pending flag remains set after the cpu completes the return-from-interrupt (reti) instruction, a new interr upt request will be gen erated immediately and the cpu will re-enter the isr after the completion of th e next instruction. 10.1. mcu interrupt sources and vectors the c8051f36x mcus support 16 interrupt sources. software can simulate an interrupt by setting any interrupt-pending fl ag to logic ?1?. if interrupts are enabled for the flag, an interrupt request will be gener - ated and the cpu will vector to th e isr address associated with the inte rrupt-pendi ng flag. mcu interrupt sources, associated vector addresses, priori ty order, and control bits are summarized in ta b l e 10.1 on page 108 . refer to the data sheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). c8051f360/1/2/3/4/5/6/7/8/9 108 rev. 1.0 10.2. interrupt priorities each interrupt source can be individually programmed to one of two priority levels: low or high. a low prior - ity interrupt service routine can be pree mpted by a high priority interrupt. a high priority interrupt cannot be preempted. each interrupt has an associated interrupt priority bit in an sfr (ip, eip1, or eip2) used to configure its priority level. low priority is the default. if two interrupts are recognized simultaneously, the interrupt with the higher priority is serviced first. if bo th interrupts have the same pr iority level, a fixed prior - ity order is used to arbitrate, given in table 10.1 . 10.3. interrupt latency interrupt response time depends on the state of the cpu when the interrupt occurs. pending interrupts are sampled and priority decoded each system clock cycle. therefore, the fastest po ssible response time is 5 system clock cycles: 1 clock cycle to detect the interrupt and 4 clock cycles to complete the lcall to the isr. additional clock cycles will be r equired if a cache miss occurs (see section 14 for more details). if an interrupt is pending when a reti is executed, a single in struction is executed before an lcall is made to service the pending interrupt. therefore, the maximum response time for an interrupt (when no other inter - rupt is currently being serviced or the new interrupt is o f greater priority) is when the cpu is performing an reti instruction followed by a div as the next instruction, and a cache miss event also occurs. if the cpu is executing an isr for an interrupt with equal or higher priority, the new interrupt will not be serviced until the current isr complete s, including the reti and following instruction. table 10.1. interrupt summary interrupt source interrupt vector priority order pending flag bit addressable? cleared by hw? enable flag priority control reset 0x0000 to p none n/a n/a always enabled always highest external interrupt 0 (/int0) 0x0003 0 ie0 (tcon.1) y y ex0 (ie.0) px0 (ip.0) timer 0 overflow 0x000b 1 tf0 (tcon.5) y y et0 (ie.1) pt0 (ip.1) external interrupt 1 (/int1) 0x0013 2 ie1 (tcon.3) y y ex1 (ie.2) px1 (ip.2) timer 1 overflow 0x001b 3 tf1 (tcon.7) y y et1 (ie.3) pt1 (ip.3) uart0 0x0023 4 ri0 (scon0.0) ti0 (scon0.1) y n es0 (ie.4) ps0 (ip.4) timer 2 overflow 0x002b 5 tf2h (tmr2cn.7) tf2l (tmr2cn.6) y n et2 (ie.5) pt2 (ip.5) spi0 0x0033 6 spif (spi0cn.7) wcol (sp i0cn.6) modf (spi0cn.5) rxovrn (spi0cn.4) y n espi0 (ie.6 ) pspi0 (ip .6) smb0 0x003b 7 si (smb0cn.0) y n esmb0 (eie 1.0) psmb0 (eip1.0) reserved 0x0043 8 n/a n/a n/a n/a n/a adc0 window comp arator 0x004b 9 ad0wint (ad c0cn.5) y n ewadc0 (eie 1.2) pwadc0 (eip1.2) adc0 end of conversion 0x0053 10 ad0int (adc0sta.5) y n eadc0 (eie 1.3) padc0 (eip1.3) rev. 1.0 109 c8051f360/1/2/3/4/5/6/7/8/9 10.4. interrupt register descriptions the sfrs used to enable the interrupt sources and set t heir priority level are described below. refer to the data sheet section associated with a particular on-chi p peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). programmable counter array 0x005b 11 cf (pca0cn.7) ccfn (pca0cn.n) y n epca0 (eie 1.4) ppca0 (eip1.4) comparator0 0x0063 12 cp0fif (cpt0cn.4) cp0rif (cp t0cn.5) n n ecp0 (eie 1.5) pcp0 (eip1.5) comparator1 0x006b 13 cp1fif (cpt1cn.4) cp1rif (cpt1cn.5) n n ecp1 (eie 1.6) pcp1 (eip1.6) timer 3 overflow 0x0073 14 tf3h (tmr3cn.7) tf3l (tmr3cn.6) n n et3 (eie 1.7) pt3 (eip1.7) reserved 0x007b 15 n/a n/a n/a n/a n/a port match 0x0083 16 n/a n/a n/a emat (eie 2.1) pmat (eip2.1) table 10.1. interrupt summary (continued) interrupt source interrupt vector priority order pending flag bit addressable? cleared by hw? enable flag priority control c8051f360/1/2/3/4/5/6/7/8/9 110 rev. 1.0 sfr definition 10.1. ie: interrupt enable bit 7: ea: global interrupt enable. this bit globally enables/disabl es all interrupts. it overrides the individual interrupt mask set- tings. 0: disable all interrupt sources. 1: enable each interrupt accord ing to its individual mask setting. bit 6: espi0: enable seri al peripheral interf ace (spi0) interrupt. this bit sets the masking of the spi0 interrupts. 0: disable all spi0 interrupts. 1: enable interrupt requests generated by spi0. bit 5: et2: enable timer 2 interrupt. this bit sets the masking of the timer 2 interrupt. 0: disable timer 2 interrupt. 1: enable interrupt requests generated by the tf2l or tf2h flags. bit 4: es0: enable uart0 interrupt. this bit sets the masking of the uart0 interrupt. 0: disable uart0 interrupt. 1: enable ua rt0 interrupt. bit 3: et1: enable timer 1 interrupt. this bit sets the masking of the timer 1 interrupt. 0: disable all ti mer 1 interrupt. 1: enable interrupt requests generated by the tf1 flag. bit 2: ex1: enable external interrupt 1. this bit sets the masking of external interrupt 1. 0: disable external interrupt 1. 1: enable interrupt requests generated by the /int1 input. bit 1: et0: enable timer 0 interrupt. this bit sets the masking of the timer 0 interrupt. 0: disable all ti mer 0 interrupt. 1: enable interrupt requests generated by the tf0 flag. bit 0: ex0: enable external interrupt 0. this bit sets the masking of external interrupt 0. 0: disable external interrupt 0. 1: enable interrupt requests generated by the /int0 input. sfr page: sfr address: all pages 0xa8 (bit addressable) r/w r/w r/w r/w r/w r/w r/w r/w reset value ea espi0 et2 es0 et1 ex1 et0 ex0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rev. 1.0 111 c8051f360/1/2/3/4/5/6/7/8/9 sfr definition 10.2. ip: interrupt priority bit 7: unused. read = 1b, write = don't care. bit 6: pspi0: serial periph eral interface (spi0) in terrupt priority control. this bit sets the priority of the spi0 interrupt. 0: spi0 interrupt set to low priority level. 1: spi0 interrupt set to high priority level. bit 5: pt2: timer 2 interrupt priority control. this bit sets the priority of the timer 2 interrupt. 0: timer 2 interrupt set to low priority level. 1: timer 2 interrupt set to high priority level. bit 4: ps0: uart0 interrupt priority control. this bit sets the priority of the uart0 interrupt. 0: uart0 interrupt set to low priority level. 1: uart0 interrupt set to high priority level. bit 3: pt1: timer 1 interrupt priority control. this bit sets the priority of the timer 1 interrupt. 0: timer 1 interrupt set to low priority level. 1: timer 1 interrupt set to high priority level. bit 2: px1: external interr upt 1 priority control. this bit sets the priority of the ex ternal interrupt 1 interrupt. 0: external interrupt 1 set to low priority level. 1: external interrupt 1 set to high priority level. bit 1: pt0: timer 0 interrupt priority control. this bit sets the priority of the timer 0 interrupt. 0: timer 0 interrupt set to low priority level. 1: timer 0 interrupt set to high priority level. bit 0: px0: external interr upt 0 priority control. this bit sets the priority of the ex ternal interrupt 0 interrupt. 0: external interrupt 0 set to low priority level. 1: external interrupt 0 set to high priority level. sfr page: sfr address: all pages 0xb8 (bit addressable) r r/w r/w r/w r/w r/w r/w r/w reset value ? pspi0 pt2 ps0 pt1 px1 pt0 px0 10000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 c8051f360/1/2/3/4/5/6/7/8/9 112 rev. 1.0 sfr definition 10.3. eie1: extended interrupt enable 1 bit 7: et3: enable timer 3 interrupt. this bit sets the masking of the timer 3 interrupt. 0: disable timer 3 interrupts. 1: enable interrupt requests generated by the tf3l or tf3h flags. bit 6: ecp1: enable comparator1 (cp1) interrupt. this bit sets the masking of the cp1 interrupt. 0: disable cp1 interrupts. 1: enable interrupt requests generated by the cp1rif or cp1fif flags. bit 5: ecp0: enable comparator0 (cp0) interrupt. this bit sets the masking of the cp0 interrupt. 0: disable cp0 interrupts. 1: enable interrupt requests generated by the cp0rif or cp0fif flags. bit 4: epca0: enable programmable counter array (pca0) interrupt. this bit sets the masking of the pca0 interrupts. 0: disable all pc a0 interrupts. 1: enable interrupt requests generated by pca0. bit 3: eadc0: enable adc0 co nversion complete interrupt. this bit sets the masking of the adc0 conversion complete interrupt. 0: disable adc0 conver sion complete interrupt. 1: enable interrupt requests generated by the ad0int flag. bit 2: ewadc0: enable adc0 window comparison interrupt. this bit sets the masking of the adc0 window comparison interrupt. 0: disable adc0 window comparison interrupt. 1: enable interrupt requests generated by the ad0wint flag. bit 1: unused. read = 0b. write = don?t care. bit 0: esmb0: enable smbu s (smb0) interrupt. this bit sets the masking of the smb0 interrupt. 0: disable all smb0 interrupts. 1: enable interrupt requests generated by smb0. sfr page: sfr address: all pages 0xe6 r/w r/w r/w r/w r/w r/w r/w r/w reset value et3 ecp1 ecp0 epca0 eadc0 ewadc0 ? esmb0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rev. 1.0 113 c8051f360/1/2/3/4/5/6/7/8/9 sfr definition 10.4. eip1: extended interrupt priority 1 bit 7: pt3: timer 3 interrupt priority control. this bit sets the priority of the timer 3 interrupt. 0: timer 3 interrupts se t to low priority level. 1: timer 3 interrupts set to high priority level. bit 6: pcp1: comparator1 (cp1) interrupt prio rity control. this bit sets the priority of the cp1 interrupt. 0: cp1 interrupt set to low priority level. 1: cp1 interrupt set to high priority level. bit 5: pcp0: comparator0 (cp0) interrupt prio rity control. this bit sets the priority of the cp0 interrupt. 0: cp0 interrupt set to low priority level. 1: cp0 interrupt set to high priority level. bit 4: ppca0: programmable counter arra y (pca0) interrupt priority control. this bit sets the priority of the pca0 interrupt. 0: pca0 interrupt set to low priority level. 1: pca0 interrupt set to high priority level. bit 3: padc0: adc0 conversion comp lete interrupt pr iority control. this bit sets the priority of the adc0 conversion complete interrupt. 0: adc0 conversion complete inte rrupt set to low priority level. 1: adc0 conversion complete inte rrupt set to high priority level. bit 2: pwadc0: adc0 window comparison interrupt priority control. this bit sets the priority of th e adc0 window comp arison interrupt. 0: adc0 window comparison inte rrupt set to low priority level. 1: adc0 window comparison interr upt set to high priority level. bit 1: unused. read = 0b. write = don?t care. bit 0: psmb0: smbus (smb0) in terrupt priority control. this bit sets the priority of the smb0 interrupt. 0: smb0 interrupt set to low priority level. 1: smb0 interrupt set to high priority level. sfr page: sfr address: f 0xce r/w r/w r/w r/w r/w r/w r/w r/w reset value pt3 pcp1 pcp0 ppca0 padc0 pwadc0 ? psmb0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 c8051f360/1/2/3/4/5/6/7/8/9 114 rev. 1.0 sfr definition 10.5. eie2: extended interrupt enable 2 bits 7?2: unused. read = 000000b. write = don?t care. bit 1: emat: enable po rt match interrupt. this bit sets the masking of the port match interrupt. 0: disable the port match interrupt. 1: enable the port match interrupt. bit 0: unused. read = 0b. write = don?t care. sfr page: sfr address: all pages 0xe7 r/w r/w r/w r/w r/w r/w r/w r/w reset value ? ? ? ? ? ? emat ? 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr definition 10.6. eip2: extended interrupt priority 2 bits 7?2: unused. read = 000000b. write = don?t care. bit 1: pmat: port match interrupt priority control. this bit sets the priority of the port match interrupt. 0: port match interrupt se t to low priority level. 1: port match interrupt se t to high priority level. bit 0: unused. read = 0b. write = don?t care. sfr page: sfr address: f 0xcf r/w r/w r/w r/w r/w r/w r/w r/w reset value ? ? ? ? ? ? pmat ? 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rev. 1.0 115 c8051f360/1/2/3/4/5/6/7/8/9 10.5. external interrupts the /int0 and /int1 external interrupt sources are configurable as active high or low, edge or level sensi - tive. the in0pl (/int0 polarity) and in1pl (/int1 polarity ) bits in the it01cf register select active high or active low; the it0 and it1 bits in tcon ( section ?21.1. timer 0 and timer 1? on page 248 ) select level or edge sensitive. the table below lis t s the possible configurations. active low, edge sensitive active low, edge sensitive active high, edge sensitive active high, edge sensitive active low, level sensitive active low, level sensitive active high, level sensitive active high, level sensitive /int0 and /int1 are assigned to port pins as defined in the it01cf register (see sfr definition 10.7). note that /int0 and /int0 port pin assignments are in dependent of any crossbar assignments. /int0 and /int1 will monitor their assigned port pins without disturbing th e peripheral that was assigned the port pin via the crossbar. to assign a port pin only to /int 0 and/or /int1, configure the crossbar to skip the selected pin(s). this is accomplished by setting the associated bit in register xbr0 (see section ?17.1. priority crossbar decoder? on page 185 for complete details on configuring the crossbar). ie0 (tcon.1) and ie1 (tcon.3) serve as the interr upt- pending flags for the /int0 and /int1 external interrupts, respectively. if an /int0 or /int1 external interrupt is configured as edge-sensitive, the corre - sponding interrupt-pending flag is automatically clear ed by the hardware when the cpu vectors to the isr. when configured as level sensitive, the interrupt-pending flag remains logic ?1? while the input is active as defined by the corresponding polarity bit (in0pl or in 1pl); the flag remains logic ?0? while the input is inac - tive. the external interrupt source must hold the input a ctive until the interrupt request is recognized. it must then deactivate the interrup t request before execution of the isr completes or another interrupt request will be generated. it0 in0pl /int0 interrupt it1 in1pl /int1 interrupt 10 10 11 11 00 00 01 01 c8051f360/1/2/3/4/5/6/7/8/9 116 rev. 1.0 sfr definition 10.7. it01cf: int0/int 1 configuration bit 7: in1pl: /int1 polarity 0: /int1 input is active low. 1: /int1 input is active high. bits 6?4: in1sl2-0: /int1 port pin selection bits these bits select which port pin is assigned to /int1. note that this pin assignment is inde- pendent of the crossbar; /int1 will monitor the assigned port pin without disturbing the peripheral that has been assi gned the port pin via the cr ossbar. the crossbar will not assign the port pin to a peripheral if it is c onfigured to skip the selected pin (accomplished by setting to ?1? the corresponding bit in register p0skip). bit 3: in0pl: /int0 polarity 0: /int0 interrupt is active low. 1: /int0 interrupt is active high. bits 2?0: int0sl2-0: /int0 port pin selection bits these bits select which port pin is assigned to /int0. note that this pin assignment is inde- pendent of the crossbar. /int 0 will monitor the assigned port pin without disturbing the peripheral that has been assi gned the port pin via the cr ossbar. the crossbar will not assign the port pin to a peripheral if it is c onfigured to skip the selected pin (accomplished by setting to ?1? the corresponding bit in register p0skip). sfr page: sfr address: all pages 0xe4 r/w r/w r/w r/w r/w r/w r/w r/w reset value in1pl in1sl2 in1sl1 in1sl0 in0pl in0sl2 in0sl1 in0sl0 00000001 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 note: refer to sfr definition 21.1. ?tcon: timer control? on page 252 for int0/1 edge- or level-sensitive interrupt selection. in1sl2-0 /int1 port pin 000 p0.0 001 p0.1 010 p0.2 011 p0.3 100 p0.4 101 p0.5 110 p0.6 111 p0.7 in0sl2-0 /int0 port pin 000 p0.0 001 p0.1 010 p0.2 011 p0.3 100 p0.4 101 p0.5 110 p0.6 111 p0.7 rev. 1.0 117 c8051f360/1/2/3/4/5/6/7/8/9 11. multiply and accumulate (mac0) the c8051f36x devices include a multiply and accumulate engine which can be used to speed up many mathematical operations. mac0 cont ains a 16-by-16 bit multiplier and a 40-bit adder, which can perform integer or fractional mult iply-accumulate and multip ly operations on signed in put values in two sysclk cycles. a rounding engi ne provides a rounded 16-bit fractional result after an additional (third) sysclk cycle. mac0 also contains a 1-bit arithmetic shifter that will left or right-shift the contents of the 40-bit accu - mulator in a single sysclk cycle. figure 11.1 shows a block diagram of the mac0 unit and its associated special function registers. mac0cf mac0ms mac0fm mac0sat mac0ca mac0sd mac0sc mac0sta mac0n mac0so mac0z mac0ho 16 x 16 multiply mac0rndh mac0rndl mac0 rounding register mac0ovr mac0acc3 mac0acc2 mac0acc1 mac0acc0 mac0 accumulator 40 bit add mac0ms 1 0 0 rounding engine 1 bit shift mac0fm flag logic mac0bh mac0bl mac0 b register mac0ah mac0al mac0 a register figure 11.1. mac0 block diagram 11.1. special function registers there are thirteen special function register (sfr) locations associated with mac0. two of these regis - ters are related to configuration and operation, while the othe r eleven are used to store multi-byte input and output data for mac0. the configuration register mac0cf ( sfr definition 11.1 ) is used to configure and control mac0. the status register mac0sta ( sfr definition 11.2 ) contains flags to indicate overflow conditions, as well as zero and negative results. the 16-bit mac0a (mac0ah:mac0al) and mac0b ( mac0bh:mac0bl) registers are used as inputs to the multiplier. the mac0 accumulator register is 40 bits long, and consists of five sfrs: ma c0ovr, mac0acc3, mac0acc2, mac0acc1, and mac0acc0. the primary results of a mac0 operation are stored in the accumulator registers. if they are needed, the rounded results are stored in the 16-bit rounding register mac0rnd (mac0rndh:mac0rndl). c8051f360/1/2/3/4/5/6/7/8/9 118 rev. 1.0 11.2. integer and fractional math mac0 is capable of interpreting t he 16-bit inputs stored in mac0a and mac0b as signed integers or as signed fractional numbers. when the mac0fm bit (mac0c f.1) is cleared to ?0?, the inputs are treated as 16-bit, 2?s complement, integer values. after the operation, the accumulator will contain a 40-bit, 2?s com - plement, integer value. figure 11.2 shows how integers are stored in the sfrs. -(2 15 ) 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 -(2 39 ) 2 38 2 33 2 32 2 31 2 30 2 1 2 0 2 2 2 29 2 3 2 28 2 4 high byte low byte mac0ovr mac0acc3 : mac0acc2 : mac0acc1 : mac0acc0 mac0a and mac0b bit weighting mac0 accumulator bit weighting figure 11.2. integer mode data representation when the mac0fm bit is set to ?1?, the inputs are treated at 16-bit, 2?s complement, fractional values. the decimal point is located between bi ts 15 and 14 of the data word. after the operation, the accumulator will contain a 40-bit, 2?s complement, fractional value, wit h the decimal point located between bits 31 and 30. figure 11.3 shows how fractional numbers are stored in the sfrs. -1 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 2 -9 2 -10 2 -11 2 -12 2 -13 2 -14 2 -15 -(2 8 ) 2 7 2 2 2 1 2 0 2 -1 2 -30 2 -31 2 -29 2 -2 2 -28 2 -3 2 -27 high byte low byte mac0ovr mac0acc3 : mac0acc2 : mac0acc1 : mac0acc0 mac0a, and mac0b bit weighting mac0 accumulator bit weighting mac0rnd bit weighting * the mac0rnd register contains the 16 lsbs of a two's complement number. the mac0n flag can be used to determine the sign of the mac0rnd register. 1 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 2 -9 2 -10 2 -11 2 -12 2 -13 2 -14 2 -15 high byte low byte * -2 figure 11.3. fractional m ode data representation rev. 1.0 119 c8051f360/1/2/3/4/5/6/7/8/9 11.3. operating in multip ly and accumulate mode mac0 operates in multiply and ac cumulate (mac) mode when the mac0ms bit (mac0cf.0) is cleared to ?0?. when operating in mac mode, mac0 performs a 16 -by-16 bit multiply on t he contents of the mac0a and mac0b registers, and adds the result to t he contents of the 40-bit mac0 accumulator. figure 11.4 shows the mac0 pipeline. th ere are three st ages in th e pipeline, each of whic h takes exactly one sysclk cycle to complete. the mac operation is initiated with a write to the mac0bl register. after the mac0bl register is written, mac0a and ma c0b are multiplied on the first syscl k cycle. during the second stage of the mac0 pipeline, the results of the multiplicati on are added to the current accumulator contents, and the result of the addition is stored in the mac0 accumulator. the status flags in the mac0sta register are set after the end of the second pipeline stage. during the second stage of the pipeline, the next multiplica - tion can be initiated by writing to the mac0bl register , if it is desired. the rounded (and optionally, satu - rated) result is available in the mac0rndh and mac0rndl registers at the end of the third pipeline st age. if the mac0ca bit (mac0cf.3) is set to ?1? when the mac operation is initiated, th e accumulator and all mac0sta flags will be cleared during the next cycle of the controller?s clock (sysclk). the mac0ca bit will clear itself to ?0? wh en the clear operation is complete. multiply add round multiply add round write mac0bl write mac0bl mac0 operation begins next mac0 operation may be initiated here accumulator results available rounded results available figure 11.4. mac0 pipeline 11.4. operating in multiply only mode mac0 operates in multiply only mo de when the mac0ms bit (mac0cf.0) is set to ?1?. mult iply only mode is identical to multiply and accumula te mode, except that the multiplicat ion result is added with a value of zero before being stored in the mac0 accumulator (i.e . it overwrites the current accumulator contents). the result of the multiplication is available in the mac0 accumulator registers at the end of the second mac0 pipeline stage (two sysclks after writing to mac0bl). as in mac mode, the rounded result is available in the mac0 rounding registers after the thir d pipeline stage. note that in multiply only mode, the mac0ho flag is not affected. 11.5. accumulator shift operations mac0 contains a 1-bit arithmetic shift function which can be used to shift the contents of the 40-bit accu - mulator left or right by one bit. the accumulator sh if t is initiated by writing a ?1? to the mac0sc bit (mac0cf.5), and takes one sysclk cycl e (the rounded result is availa ble in the mac0 rounding regis - ters after a second sysclk cycle, a nd mac0sc is cleared to ?0?). the di rection of the arithmetic shift is controlled by the mac0sd bit (mac0cf. 4). when this bit is cleared to ?0?, the mac0 ac cumulator will shift left. when the mac0sd bit is set to ?1?, the mac0 accumulator will shift right. right-shift operations are sign-extended with the current value of bit 39. note t hat the status flags in the mac0sta register are not affected by shift operations. c8051f360/1/2/3/4/5/6/7/8/9 120 rev. 1.0 11.6. rounding and saturation a rounding engine is included, wh ich can be used to provide a rounded result when operating on frac - tional numbers. mac0 uses an un biased rounding algorithm to round the data stored in bits 31 ? 16 of the accumulator, as shown in table 11.1 . rounding occurs during the third stage of the mac0 pipeline, after any shift operation, or on a write to the lsb of the accumulator. the rounded results are stored in the rounding registers : mac0rndh ( sfr definition 11.12 ) and mac0rndl ( sfr definition 11.13 ). the accu - mulator registers are not affected by the rounding engi ne . although rounding is primarily used for fractional data, the data in the rounding registers is updated in the same way when operating in integer mode. table 11.1. mac0 rounding (mac0sat = 0) accumulator bits 15?0 (mac0acc1:mac0acc0) accumulator bits 31?16 (mac0ac c3:mac0acc2) rounding di rection rounded results (mac 0rndh:mac0rndl) greater than 0x8000 anything up (mac0acc3:mac0acc2) + 1 less than 0x8000 anything down (mac0acc3:mac0acc2) equal to 0x8000 odd (lsb = 1) up (mac0acc3:mac0acc2) + 1 equal to 0x8000 even (lsb = 0) down (mac0acc3:mac0acc2) the rounding engine can also be used to saturate the results stored in the rounding registers. if the mac0sa t bit is set to ?1? and the ro unding register overflows, the roun ding registers w ill saturate. when a positive overflow occurs , the rounding registers will show a value of 0x7fff wh en saturated. for a nega - tive overflow, the rounding registers will show a valu e of 0x 8000 when saturated. if the mac0sat bit is cleared to ?0?, the rounding registers will not saturate. 11.7. usage examples this section details some software examples for us ing mac0. section 11.7.1 shows a series of two mac operations using fractional numbers. section 11.7.2 shows a single operation in multiply only mode with integer numbers. the last example, shown in section 11.7.3 , demonstrates how the left-shift and right-shift operations can be used to modify the accumulator. all of th e examples assume that all of the flags in the mac0sta register are initially set to ?0?. 11.7.1. multiply and accumulate example the example below implements the equation: 0.5 0.25 () 0.5 0.25 ? () + 0.125 0.125 ?0.0 == mov mac0cf, #0ah ; set to clear accumulator, use fractional numbers mov mac0ah, #40h ; load mac0a register with 4000 hex = 0.5 decimal mov mac0al, #00h mov mac0bh, #20h ; load mac0b register with 2000 hex = 0.25 decimal mov mac0bl, #00h ; this line initiates the first mac operation mov mac0bh, #e0h ; load mac0b register with e000 hex = -0.25 decimal mov mac0bl, #00h ; this line initiates the second mac operation nop nop ; after this instruction, the accumulator should be equal to 0, ; and the mac0sta register should be 0x04, indicating a zero nop ; after this instruction, the rounding register is updated rev. 1.0 121 c8051f360/1/2/3/4/5/6/7/8/9 11.7.2. multiply only example the example below implements the equation: 4660 292? 1360720?= mov mac0cf, #01h ; use integer numbers, and multiply only mode (add to zero) mov mac0ah, #12h ; load mac0a register with 1234 hex = 4660 decimal mov mac0al, #34h mov mac0bh, #feh ; load mac0b register with fedc hex = -292 decimal mov mac0bl, #dch ; this line initiates the multiply operation nop nop ; after this instruction, the accumulator should be equal to ; ffffeb3cb0 hex = -1360720 decimal. the mac0sta register should ; be 0x01, indicating a negative result. nop ; after this instruction, the rounding register is updated 11.7.3. mac0 accumulator shift example the example below shifts the mac0 accumulator left one bit, and then right two bits: mov mac0ovr, #40h ; the next few instructions load the accumulator with the value mov mac0acc3, #88h ; 4088442211 hex. mov mac0acc2, #44h mov mac0acc1, #22h mov mac0acc0, #11h mov mac0cf, #20h ; initiate a left-shift nop ; after this instruction, the accumulator should be 0x8110884422 nop ; the rounding register is updated after this instruction mov mac0cf, #30h ; initiate a right-shift mov mac0cf, #30h ; initiate a second right-shift nop ; after this instruction, the accumulator should be 0xe044221108 nop ; the rounding register is updated after this instruction c8051f360/1/2/3/4/5/6/7/8/9 122 rev. 1.0 sfr definition 11.1. mac0cf: mac0 configuration bits 7 ? 6: unused: read = 00b, write = don?t care. bit 5: mac0sc: accumu lator shift control. when set to 1, the 40-bit ma c0 accumulator register will be shifted during the next sysclk cycle. the direction of the shift (left or right) is controlled by the mac0sd bit. this bit is cleared to ?0? by hardware when the shift is complete. bit 4: mac0sd: accumulator shift direction. this bit controls the direction of the accu mulator shift activated by the mac0sc bit. 0: mac0 accumulator will be shifted left. 1: mac0 accumulator will be shifted right. bit 3: mac0ca: clear accumulator. this bit is used to reset mac0 before the next operation. when set to ?1?, the mac0 accumulator will be cl eared to zero and the mac0 status register will be reset during the next sysclk cycle. this bit will be cleared to ?0? by ha rdware when the reset is complete. bit 2: mac0sat: saturate rounding register. this bit controls whether the rounding register will saturate. if this bit is set and a soft overflow occurs, the rounding register will satu rate. this bit does not affect the operation of the mac0 accumulator. see section 11.6 for more details about rounding and saturation. 0: rounding register will not saturate. 1: rounding regi ster will saturate. bit 1: mac0fm: fractional mode. this bit selects between integer mode and fractional mode for mac0 operations. 0: mac0 operates in integer mode. 1: mac0 operates in fractional mode. bit 0: mac0ms: mode select this bit selects between mac mo de and multiply only mode. 0: mac (multiply and accumulate) mode. 1: multiply only mode. note: the contents of this register should not be changed by software during the first two mac0 pipeline stages. sfr page: sfr address: 0 0xd7 r r r/w r/w r/w r/w r/w r/w reset value ? ? mac0sc mac0sd mac0ca mac0sat mac0fm mac0ms 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rev. 1.0 123 c8051f360/1/2/3/4/5/6/7/8/9 sfr definition 11.2. mac0sta: mac0 status bits 7 ? 4: unused: read = 0000b, write = don?t care. bit 3: mac0ho: hard overflow flag. this bit is set to ?1? whenever an overflow out of the mac0ovr register occurs during a mac operation (i.e. when mac0ovr changes from 0x7f to 0x80 or from 0x80 to 0x7f). the hard overflow flag must be cleared in software by directly writing it to ?0?, or by resetting the mac logic using the mac0ca bit in register mac0cf. bit 2: mac0z: zero flag. this bit is set to ?1? if a mac0 operation result s in an accumulator value of zero. if the result is non-zero, this bit will be cleared to ?0?. bit 1: mac0so: soft overflow flag. this bit is set to ?1? when a mac operation causes an overflow into the sign bit (bit 31) of the mac0 accumulator. if the overflow condition is corrected after a subsequent mac operation, this bit is cleared to ?0?. bit 0: mac0n: negative flag. if the mac accumulator result is negative, this bit wi ll be set to ?1?. if th e result is positive or zero, this flag will be cleared to ?0?. note: the contents of this register should not be changed by software during the first two mac0 pipeline stages. sfr page: sfr address: 0 0xcf r r r r r/w r/w r/w r/w reset value ? ? ? ? mac0ho mac0z mac0so mac0n 00000100 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr definition 11.3. mac0ah: mac0 a high byte bits 7 ? 0: high byte (bits 15 ? 8) of mac0 a register. sfr page: sfr address: 0 0xa5 rrrrrrrrr e s e t v a l u e 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 c8051f360/1/2/3/4/5/6/7/8/9 124 rev. 1.0 sfr definition 11.4. mac0al: mac0 a low byte bits 7 ? 0: low byte (bits 7 ? 0) of mac0 a register. sfr page: sfr address: 0 0xa4 rrrrrrrrr e s e t v a l u e 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr definition 11.5. mac0bh: mac0 b high byte bits 7 ? 0: high byte (bits 15 ? 8) of mac0 b register. sfr page: sfr address: 0 0xf2 rrrrrrrrr e s e t v a l u e 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr definition 11.6. mac0bl: mac0 b low byte bits 7 ? 0: low byte (bits 7 ? 0) of mac0 b register. a write to this register initiates a multip ly or multiply and accumulate operation. note: the contents of this register should not be changed by software during the first mac0 pipeline stage. sfr page: sfr address: 0 0xf1 rrrrrrrrr e s e t v a l u e 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rev. 1.0 125 c8051f360/1/2/3/4/5/6/7/8/9 sfr definition 11.7. mac0acc3: mac0 accumulator byte 3 bits 7 ? 0: byte 3 (bits 31 ? 24) of mac0 accumulator. note: the contents of this register should not be changed by software during the first two mac0 pipeline stages. sfr page: sfr address: 0 0xd5 rrrrrrrrr e s e t v a l u e 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr definition 11.8. mac0acc2: mac0 accumulator byte 2 bits 7 ? 0: byte 2 (bits 23 ? 16) of mac0 accumulator. note: the contents of this register should not be changed by software during the first two mac0 pipeline stages. sfr page: sfr address: 0 0xd4 rrrrrrrrr e s e t v a l u e 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr definition 11.9. mac0acc1: mac0 accumulator byte 1 bits 7 ? 0: byte 1 (bits 15 ? 8) of mac0 accumulator. note: the contents of this register should not be changed by software during the first two mac0 pipeline stages. sfr page: sfr address: 0 0xd3 rrrrrrrrr e s e t v a l u e 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 c8051f360/1/2/3/4/5/6/7/8/9 126 rev. 1.0 sfr definition 11.10. mac0acc0: mac0 accumulator byte 0 bits 7 ? 0: byte 0 (bits 7 ? 0) of mac0 accumulator. note: the contents of this register should not be changed by software during the first two mac0 pipeline stages. sfr page: sfr address: 0 0xd2 rrrrrrrrr e s e t v a l u e 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr definition 11.11. mac0ovr: mac0 accumulator overflow bits 7 ? 0: mac0 accumulator overflow bits (bits 39 ? 32). note: the contents of this register should not be changed by software during the first two mac0 pipeline stages. sfr page: sfr address: 0 0xd6 rrrrrrrrr e s e t v a l u e 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr definition 11.12. mac0rndh: mac0 roundi ng register high byte bits 7 ? 0: high byte (bits 15 ? 8) of mac0 rounding register. sfr page: sfr address: 0 0xaf rrrrrrrrr e s e t v a l u e 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rev. 1.0 127 c8051f360/1/2/3/4/5/6/7/8/9 sfr definition 11.13. mac0rndl: mac0 roundi ng register low byte bits 7 ? 0: low byte (bits 7 ? 0) of mac0 rounding register. sfr page: sfr address: 0 0xae rrrrrrrrr e s e t v a l u e 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 c8051f360/1/2/3/4/5/6/7/8/9 128 rev. 1.0 12. reset sources reset circuitry allows the controller to be easily placed in a predefined default condition. on entry to this reset state, th e following occur: ? cip-51 halts program execution ? special function registers (sfrs) are initialized to their defined reset values ? external port pins are forced to a known state ? interrupts and timers are disabled. all sfrs are reset to the predefined values noted in the sfr detailed descriptions. the contents of internal d ata memory are unaffected during a reset; any prev iously stored data is preserved. however, since the stack pointer sfr is reset, the stack is effectively lo st, even though the data on the stack is not altered. the port i/o latches are reset to 0xff (all logic ones) in open-drain mode. weak pullups are enabled dur - ing and after the reset. for v dd monitor and power-on resets, the rst pin is driven low until the device exits the reset state. on exit from the reset state, the program counter (pc) is reset, and the system clock defaults to the inter - nal oscillator. refer to section ?16. oscillators? on page 169 for information on se lectin g and configuring the system clock source. the watchdog timer is enabled with the system clock divide d by 12 as its clock source ( section ?22.3. watchdog timer mode? on page 272 details the use of the watchdog timer). pro - gram execution begins at location 0x0000. pca wdt missing clock detector (one- shot) (software reset) system reset reset funnel px.x px.x en swrsf system clock cip-51 microcontroller core extended interrupt handler en wdt enable mcd enable errant flash operation /rst (wired-or) power on reset '0' + - comparator 0 c0rsef vdd + - supply monitor enable figure 12.1. reset sources rev. 1.0 129 c8051f360/1/2/3/4/5/6/7/8/9 12.1. power-on reset during power-up, the device is held in a reset state and the rst pin is driven low until v dd settles above v rst . a delay occurs before the device is released from reset; the delay decreases as the v dd ramp time increases (v dd ramp time is defined as how fast v dd ramps from 0 v to v rst ). figure 12.2 . plots the power-on and v dd monitor reset timing. for ramp times less than 1 ms, the power-on reset delay (t porde - lay ) is typically less than 0.3 ms. note: t he maximum v dd ramp time is 1 ms; slower ramp times may cause the device to be released from r eset before v dd reaches the v rst level. on exit from a power-on reset, the porsf flag (rst src.1) is set by hardware to logic ?1?. when porsf is set, all of the other reset flags in the rstsrc regi ster are indeterminate (porsf is cleared by all other resets). since all resets cause program execution to begin at the same location (0x0000) software can read the porsf flag to determine if a power-up was t he cause of reset. the content of internal data mem - ory should be assumed to be undefined after a power-on reset. the v dd monitor is enabled following a power-on reset. power-on reset vdd monitor reset /rst t volts 1.0 2.0 logic high logic low t pordelay v d d 2.70 2.55 v rst vdd figure 12.2. power-on and v dd monitor reset timing c8051f360/1/2/3/4/5/6/7/8/9 130 rev. 1.0 12.2. power-fail reset/v dd monitor when a power-down transition or power irregularity causes v dd to drop below v rst , the power supply monitor will drive the rst pin low and hold the cip-51 in a reset state (see figure 12.2 ). when v dd returns to a level above v rst , the cip-51 will be released from the reset state. note that even though internal data memory contents are not altered by the power-fa il reset, it is impossib le to determine if v dd dropped below the level required for data retention. if the porsf flag reads ?1?, the data may no longer be valid. the v dd monitor is enabled after power-on resets; however its defi ned state (enabled/disabled) is not altered by any other reset source. for example, if the v dd monitor is disabled and a software reset is performed, the v dd monitor will still be disabled after the reset. to protect the integrity of flash contents, the v dd monitor must be enabled and selected as a reset source if software contains routines which erase or write flash memory. if the v dd monitor is not enabled, any erase or write performed on flash memory will cause a flash error device reset. the v dd monitor must be enabled before it is selected as a reset source. selecting the v dd monitor as a reset source before it is enabl ed and stabilized may cause a system reset. the procedure for config - uring the v dd monitor as a reset so urce is shown below: step 1. enable the v dd monitor (vdmen bit in vdm0cn = ?1?). step 2. wait for the v dd monitor to stabilize (a pproximately 5 s). note: this delay should be omitted if software contains routines which erase or write flash memory . step 3. select the v dd monitor as a reset source (porsf bit in rstsrc = ?1?). see table 12.1 for complete electrical charac teristics of the v dd monitor. note: software should take care not to inadvertently disable the v dd monitor as a reset source when writing to rstsrc to enable other reset sources or to trigger a software reset. all writes to rstsrc should explicitly set porsf to '1' to keep the v dd monitor enabled as a reset source. rev. 1.0 131 c8051f360/1/2/3/4/5/6/7/8/9 sfr definition 12.1. vdm0cn: v dd monitor control bit 7: vdmen: v dd monitor enable. this bit turns the v dd monitor circuit on/off. the v dd monitor cannot generate system resets until it is also selected as a reset source in register rstsrc (sfr definition 12.2). the v dd monitor must be allowed to stabilize before it is selected as a reset source. selecting the v dd monitor as a reset source before it has stabilized may generate a system reset. 0: v dd monitor disabled. 1: v dd monitor enabled. bit 6: v dd stat: v dd status. this bit indicates the current power supply status (v dd monitor output). 0: v dd is at or below the v dd monitor threshold. 1: v dd is above the v dd monitor threshold. bits 5?0: reserved. read = variable. write = don?t care. sfr page: sfr address: all pages 0xff r / wr rrrrr rr e s e t v a l u e vdmen vddstat reserved reserved reserved reserved reserved reserved variable bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 12.3. external reset the external rst pin provides a means for external circuitry to force the device into a reset state. assert - ing an active-low signal on the rst pin generates a reset; an external pullup and/or decoupling of the rst pin may be necessary to avoid erroneous noise-induced resets. see table 12.1 for complete rst pin specifications. the pinrsf flag (rstsrc.0) is set on exit from an external reset. 12.4. missing clock detector reset the missing clock detector (mcd) is a one-shot circuit that is triggered by the syst em clock. if the system clock remains high or low for more than 100 s, the one-shot will time out an d generate a reset. after a mcd reset, the mcdrsf flag (rstsrc.2) will read ?1?, signifying the mcd as the reset source; otherwise, this bit reads ?0?. writing a ?1? to the mcdrsf bit enables the missing clock detector; writing a ?0? disables it. the state of the rst pin is unaffected by this reset. 12.5. comparator0 reset comparator0 can be configured as a reset source by writing a ?1? to the c0rsef flag (rstsrc.5). comparator0 should be enabled and allowed to settle prior to writing to c0rsef to prevent any turn-on chatter on the output from generating an unwanted rese t. the comparator0 reset is active-low: if the non- inverting input voltage (on cp0+) is le ss than the inverting input voltage (on cp0-), the device is put into the reset state. afte r a comparator0 reset, the c0rsef flag (rstsrc.5) will read ?1? signifying comparator0 as the reset source; otherwise, this bit reads ?0?. the state of the rst pin is unaffected by this reset. c8051f360/1/2/3/4/5/6/7/8/9 132 rev. 1.0 12.6. pca watchdog timer reset the programmable watchdog timer (wdt) function of the programmable counter array (pca) can be used to prevent software from running out of cont rol during a system malfunction. the pca wdt function can be enabled or disabled by software as described in section ?22.3. watchdog timer mode? on page 272 ; the wdt is enabled and clocked by sysclk / 12 following any reset. if a system malfunction prevents user software from updating the wdt, a re set is gen erated and the wdtrsf bit (rstsrc.5) is set to ?1?. the state of the rst pin is unaffected by this reset. 12.7. flash error reset if a flash read/write/era se or program read targets an illegal address, a system reset is generated. this may occur due to any of the following: ? a flash write or erase is attempted above user code space. this occurs when pswe is set to ?1? and a movx write operation targets an address above address 0x7bff. ? a flash read is attempted above user code space. this occurs when a movc operation targets an address above address 0x7bff. ? a program read is attempted above user code spac e. this occu rs when user code attempts to branch to an address above 0x7bff. ? a flash read, write or erase attempt is re stricted d ue to a flash security setting (see section ?13.2. security options? on page 138 ). ? a flash write or erase is attempted while the v dd monitor is disabled. the ferror bit (rstsrc.6) is set following a flash error reset. the state of the rst pin is unaffected by this reset. 12.8. software reset software may force a reset by writing a ?1? to the swrsf bit (rstsrc.4). the swrsf bit will read ?1? fol - lowing a software forced reset. the state of the rst pin is unaffected by this reset. rev. 1.0 133 c8051f360/1/2/3/4/5/6/7/8/9 sfr definition 12.2. rstsrc: reset source note: for bits that act as both reset source enables (on a write) and reset indicator flags (on a read), read-modify-write instructions read and modify the source enable only. [this applies to bits: c0rsef, swrsf, mcdrsf, porsf]. bit 7: unused. read = 0b. write = don?t care. bit 6: ferror: flash error indicator. 0: source of last reset was not a flash read/write/erase error. 1: source of last reset was a flash read/write/erase error. bit 5: c0rsef: comparator0 reset enable and flag. 0: read: source of last reset was not comparator0. write: comparator0 is not a reset source. 1: read: source of last reset was comparator0. write: comparator0 is a reset source (active-low). bit 4: swrsf: software reset force and flag. 0: read: source of last reset was not a write to the swrsf bit. write: no effect. 1: read: source of last reset was a write to the swrsf bit. write: forces a system reset. bit 3: wdtrsf: watchdog timer reset flag. 0: source of last reset was not a wdt timeout. 1: source of last reset was a wdt timeout. bit 2: mcdrsf: missing clock detector flag. 0: read: source of last reset was not a missing clock detector timeout. write: missing clock detector disabled. 1: read: source of last reset was a mi ssing clock detector timeout. write: missing clock detector enabled; triggers a reset if a missing clock condition is detected. bit 1: porsf: power-on reset force and flag. this bit is set anytime a power-on reset occurs. writing this bit enables/disables the v dd monitor as a reset source. note: writing ?1? to this bit before the v dd monitor is enabled and stabilized may cause a system reset. see register vdm0cn (sfr definition 12.1) 0: read: last reset was not a power-on or v dd monitor reset. write: v dd monitor is not a reset source. 1: read: last reset was a power-on or v dd monitor reset; all other reset flags indeterminate. write: v dd monitor is a reset source. bit 0: pinrsf: hw pin reset flag. 0: source of last reset was not rst pin. 1: source of la st reset was rst pin. sfr page: sfr address: all pages 0xef r r r/w r/w r r/w r/w r reset value ? ferror c0rsef swrsf wdtrsf mcdrsf porsf pinrsf variable bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 table 12.1. reset electrical characteristics ?40 to +85 c unless otherwise specified. c8051f360/1/2/3/4/5/6/7/8/9 134 rev. 1.0 parameter conditions min typ max units rst output low voltage i ol = 8.5 ma, v dd = 2.7 v to 3.6 v ??0.6v rst input high voltage 0.7 x v dd ?? v rst input low voltage ? ? 0.7 v rst input pullup impedance ? 100 ? k ? v dd por threshold (v rst ) 2.40 2.55 2.70 v missing clock detector time- out time from last system clock rising edge to reset initiation 100 220 600 s reset time delay delay between release of any reset source and code execution at location 0x0000 40 ? ? s minimum rst low time to generate a system reset 15 ? ? s v dd monitor supply current ?1940a rev. 1.0 135 c8051f360/1/2/3/4/5/6/7/8/9 13. flash memory all devices include either 32 kb (c8051f360/1/2/3/4/5/6 /7) or 16 kb (c8051f368/9) of on-chip, reprogram - mable flash memory for program code or non-volat ile data storage. the flash memory can be pro - grammed in-system through the c2 interface, or by so ftware using the movx write instructions. once cleared to logic ?0?, a flash bit must be erased to se t it back to logic ?1?. bytes should be erased (set to 0xff) before being reprogrammed. flash write and er ase operations are automatically timed by hardware for proper execution. during a flash erase or write, the flbusy bit in the flstat register is set to ?1? (see sfr definition 14.5 ). during this time, instructions that are locate d in the prefetch buffer or the branch target cache can be executed, but the processor will stall until the eras e or write is completed if instruction data must be fetched from flash memory. interrupts that have been pre-loaded into the branch target cache can also be serviced at this time, if the current code is also ex ecuting from the prefetch engine or cache memory. any interrupts that are not pre- loaded into cache, or that occur while th e core is halted, will be held in a pending state during the flash write/erase operation, and serviced in priority order once the flash operation has co mpleted. refer to ta b l e 13.2 for the electrical characte rist ics of the flash memory. 13.1. programming the flash memory the simplest means of programming the flash memory is through the c2 interface using programming tools provided by silicon labs or a third party vendor. this is the only means for programming a non-initial - ized device. for details on the c2 commands to program flash memory, see section ?24. c2 interface? on page 284 . for detailed guidelines on writing or er asing flash from firmware, please see section ?13.3. flash write and erase guidelines? on page 140 . the flash memory can be programmed from software using the movx write instruction with the address a nd data byte to be programmed provided as norma l operands. before writing to flash memory using movx, flash write operations must be enabled by setting the pswe program store write enable bit (psctl.0) to logic ?1?. th is directs the movx writes to flash memo ry instead of to xram, which is the default target. the pswe bit remains set until cleared by software. to avoid errant flash writes, it is rec - ommended that interrupts be disa bled while the pswe bit is logic ?1?. flash memory is read using the movc instruction. movx re ads are always directed to xram, regardless of the state of pswe. note: to ensure the integrity of the flash contents, the on-chip v dd monitor must be enabled in any system that includes code that writes and/or erases flash memory from software. furthermore, there should be no delay between enabling the v dd monitor and enabling the v dd monitor as a reset source. any attempt to write or erase flash memory while the v dd monitor disabled will cause a flash error device reset. a write to flash memory can clear bits but cannot set the m; only an erase operation can set bits in flash. a byte location to be programmed must be erased before a new value can be written . write/erase timing is automatically cont ro lled by hardware. note that on the 32 k flash devices, 1024 by tes beginning at location 0x7c00 are reserved. flash writes and erases targeting the reserved area should be avoided. 13.1.1. flash lock and key functions flash writes and erases by user so ftware are protected with a lock and key function. the flash lock and key register (flkey) must be writ ten with the correct key codes, in sequence, be fore flash operations may be performed. the key codes are: 0xa5, 0xf1. the timing does not matter, but the codes must be written in order. if the key codes are written out of or der, or the wrong codes are written, flash writes and c8051f360/1/2/3/4/5/6/7/8/9 136 rev. 1.0 erases will be disabled until the next system reset. flash writes and eras es will also be disabled if a flash write or erase is attempted before the key codes have been written properly. the flash lock resets after each write or erase; the key codes must be writte n again before a following flash operation can be per - formed. the flkey regist er is det ailed in sfr definition 13.2 . 13.1.2. erasing flash pages from software the flash memory can be programmed by software using the movx write instruction with the address and data byte to be programmed provided as normal operands. before writing to flash memory using movx, flash write operations must be enabled by: (1) the pswe and psee bits must be set to ?1? (this directs the movx writes to target flash memory); and (2) writin g the flash key codes in sequence to the flash lock register (flkey). the pswe bit remains set until cleared by software. a write to flash memory can clear bits to logic ?0? bu t cannot set them; only an er ase operation can set bits to logic ?1? in flash. a byte location to be programmed should be erased before a new value is writ - ten. the flash memory is organized in 1024-byte pages. the erase operation applies to an entire page (setting all bytes in the page to 0xff). to erase an entire 1024-byte page, perform the following steps: step 1. disable interrupts (recommended). s tep 2. write the first key code to flkey: 0xa5. step 3. write the second key code to flkey: 0xf1. step 4. set psee (psctl.1) to enable flash erases. step 5. set pswe (psctl.0) to redire ct movx commands to write to flash. step 6. use the movx instruction to write a data byte to any location within the page to be erased. step 7. clear psee to disable flash erases. step 8. clear the pswe bit to redirect movx commands to the xram data space. step 9. re-enable interrupts. 13.1.3. writing flash memory from software bytes in flash memory can be written one byte at a time, or in small blocks. the chblkw bit in register cch0cn ( sfr definition 14.1 ) controls whether a single byte or a bl o ck of bytes is written to flash during a write operation. when chblkw is cleared to ?0?, the flash will be wr itten one byte at a time. when chblkw is set to ?1?, the flash will be written in blocks of four bytes fo r addresses in code space. block writes are performed in the same amo unt of time as single byte writes , which can save time when storing large amounts of data to flash memory. for single-byte writes to flash, by tes ar e written individually, and the flash write is performed after each movx write instruction. the recommended procedure fo r writing flash in single bytes is as follows: step 1. disable interrupts. s tep 2. clear chblkw (register cch0cn) to select single-byte write mode. step 3. write the first key code to flkey: 0xa5. step 4. write the second key code to flkey: 0xf1. step 5. set pswe (register psctl) to re direct movx commands to write to flash. step 6. clear the psee bit (register psctl). step 7. use the movx instruction to write a data byte to the desired location (repeat as necessary). step 8. clear the pswe bit to redirect movx commands to the xram data space. step 9. re-enable interrupts. rev. 1.0 137 c8051f360/1/2/3/4/5/6/7/8/9 steps 3?8 must be repeated for each byte to be written for block flash writes, the flash write procedure is only performed after the last byte of each block is writ - ten with the movx write instruction. whe n writing to addresses located in any of the four code banks, a flash write block is four bytes long, from addresses e nding in 00b to addresses ending in 11b. writes must be performed sequentially (i.e. addresses ending in 0 0b, 01b, 10b, and 11b must be written in order). the flash write will be performed following the movx write that targets the ad dress ending in 11b. the flash write will be performed followi ng the movx write that targets the addre ss ending in 1b. if any bytes in the block do not need to be updated in flash, they should be written to 0xff. the recommended procedure for writing flash in blocks is as follows: step 1. disable interrupts. s tep 2. set chblkw (register cch0c n) to select block write mode. step 3. write the first key code to flkey: 0xa5. step 4. write the second key code to flkey: 0xf1. step 5. set pswe (register psctl) to re direct movx commands to write to flash. step 6. clear the psee bit (register psctl). step 7. using the movx instruction, write the first data byte to t he first block location (ending in 00b). step 8. clear the pswe bit to redirect movx commands to the xram data space. step 9. write the first key code to flkey: 0xa5. step 10. write the second key code to flkey: 0xf1. step 11. set pswe (register psctl) to r edirect movx commands to write to flash. step 12. clear the psee bit (register psctl). step 13. using the movx instructio n, write the second data byte to the second block location (ending in 01b). step 14. clear the pswe bit to redirect movx commands to the xram data space. step 15. write the first key code to flkey: 0xa5. step 16. write the second key code to flkey: 0xf1. step 17. set pswe (register psctl) to re direct movx commands to write to flash. step 18. clear the psee bit (register psctl). step 19. using the movx instruction, write the third data byte to the third block location (ending in 10b). step 20. clear the pswe bit to redirect movx commands to the xram data space. step 21. write the first key code to flkey: 0xa5. step 22. write the second key code to flkey: 0xf1. step 23. set pswe (register psctl) to re direct movx commands to write to flash. step 24. clear the psee bit (register psctl). step 25. using the movx instruction, write the four th data byte to the last block location (ending in 11b). step 26. clear the pswe bit to redirect movx commands to the xram data space. step 27. re-enable interrupts. steps 3-26 must be repeated for each block to be written. 13.1.4. non-volatile data storage the flash memory can be used for non-volatile data storage as well as program code. this allows data such as calibration coefficients to be calculated and st ored at run time. data is written and erased using the movx write instructio n (as described in section 13.1.2 and section 13.1.3 ) and read using the movc instruction. note: mo vx read instructions always target xram. c8051f360/1/2/3/4/5/6/7/8/9 138 rev. 1.0 13.2. security options the cip-51 provides security options to protect the flash memory from inadvertent modification by soft - ware as well as to prevent the viewing of proprietary program code and constants. the program store w rite enable (bit pswe in register psctl) and the program store erase enable (bit psee in register psctl) bits protect the flash memory from accidental modification by software. pswe must be explicitly set to ?1? before software can modify the flash me mory; both pswe and psee must be set to ?1? before software can erase flash memory. additional security features prevent proprietary program code and data constants from being read or altered across the c2 interface. a security lock byte located at the last byte of fl ash user space offers protection of the flash program memory from access (reads, writes, or erases) by unpr otected code or the c2 inte rface. the flash security mechanism allows the user to lock n 1024-byte flash pages, starting at page 0 (addresses 0x0000 to 0x 03ff), where n is the 1?s complement number represented by the security lock byte. note that the page containing the flash security lock byte is unlocked when no other flash pages are locked (all bits of the lock byte are ?1?) and locked when any other flash pages are locked (any bit of the lock byte is ?0?). see the example below for an c8051f360. access limit set according to the flash security lock byte 0x0000 0x3fff lock byte reserved 0x3ffe 0x4000 flash memory organized in 1024-byte pages 0x3c00 unlocked flash pages locked when any other flash pages are locked 0x0000 0x7bff lock byte reserved 0x7bfe 0x7c00 0x7800 unlocked flash pages ?f360/1/2/3/4/5/6/7 'f368/9 figure 13.1. flash program memory map security lock byte: 11111101b 1?s complement: 00000010b flash pages locked: 3 (first two flash pages + lock byte page) addresses locked: 0x0000 to 0x07ff (first two flash pages) and 0x7800 to 0x7bff (lock byte page) rev. 1.0 139 c8051f360/1/2/3/4/5/6/7/8/9 13.2.1. summary of flash security options the level of flash security depends on the flash ac cess method. the three flash access methods that can be restricted are reads, writes, an d erases from the c2 debug interface, user firmware executing on unlocked pages, and user firmware executing on locked pages. ta b l e 13.1 summarizes the flash security features of the c8051f36x devices. table 13.1. flash security summary action c2 debug interface user firmware executing from: an unlocked page a locked page read, write or erase unlocked pages ( except page with lock byte) permitted permitted permitted read, write or erase locked pages ( except page with lock byte) not permitted fedr permitted read or write page containing lock byte ( if no pages are locked) permitted permitted permitted read or write page containing lock byte (if an y page is locked) not permitted fedr permitted read contents of lock byte (if no pages are locked) permitted permitted permitted read contents of lock byte (if any page is locked) not permitted fedr permitted erase page containing lock byte ( if no pages are locked) permitted fedr fedr erase page containing lock byte - unlock all pages (if an y page is locked) only c2de fedr fedr lock additional pages (cha nge '1's to '0's in the lock byte) not permitted fedr fedr unlock individual pages (change '0's to '1's in the lock byte) not permitted fedr fedr read, write or erase reserved area not permitted fedr fedr c2de - c2 device erase (erases all flash pages including the page containing the lock byte) fedr - not permitted; causes flash error device res et (ferror bit in rstsrc is '1' after reset) - all prohibited operations that are performed via the c2 in terface are ignored (do not cause device reset). - locking any flash page also locks th e page containing the lock byte. - once written to, the lock byte cannot be modifi e d except by performing a c2 device erase. - if user code writes to the lock byte, the lock do es not take effect until the next device reset. c8051f360/1/2/3/4/5/6/7/8/9 140 rev. 1.0 13.3. flash write and erase guidelines any system which contains routines which write or er ase flash memory from software involves some risk that the write or erase ro utines will execute unin tentionally if the cpu is op erating outside its specified operating range of v dd , system clock frequency, or temperature. this accidental execution of flash modi - fying code can result in alteration of flash memory conte nts causing a system failure that is only recover - able by re-flashing the code in the device. to help prevent the accidental modifi ca tion of flash by firmware, the v dd monitor must be enabled and enabled as a reset source on c8051f36x devices for the flash to be successfully modified. if either the v dd monitor or the v dd monitor reset source is not enabled, a flash error device reset will be gen - erated when the firmware attempts to modify the flash. the following guidelines are recomme nded f or any system that contains routines which write or erase flash from code. 13.3.1. v dd maintenance and the v dd monitor 1. if the system power supply is subject to volta ge or current "spikes," add sufficient transient protection devices to the power supply to ensure that the supply voltages listed in the absolute maximum ratings table are not exceeded. 2. make certain that the minimum v dd rise time specification of 1 ms is met. if the system cannot meet this rise time specific ation, then add an external v dd brownout circuit to the /rst pin of the device that holds the device in reset until v dd reaches v rst and re-asserts /rst if v dd drops below v rst . please see ta b l e 12.1, ?reset electrical characteristics,? on page 134 for more information on the vdd monitor threshold voltage (v rst ). 3. keep the on-chip v dd monitor enabled and enable the v dd monitor as a reset source as early in code as possible. this should be the first set of instructions executed after the reset vector. for 'c'-based systems, this will involve modifying the startup co de added by the 'c' compiler. see your compiler documentation for more details. make certain that there are no delays in software between enabling the v dd monitor and enabling the v dd monitor as a reset source. code examples showing this can be found in an 201, "writing to flash from firmware", avail - able from the silicon laboratories web site. note: on c8051f36x devices, both the v dd monitor and the v dd monitor reset source must be enabled to write or erase flash witho ut generating a flash error device reset. 4. as an added precaution, explicitly enable the v dd monitor and enable the v dd monitor as a reset source inside the functions that write and erase flash memory. the v dd monitor enable instructions should be placed just after the in struction to set pswe to a '1', but before the flash write or erase operation instruction. 5. make certain that all writes to the rstsrc (r eset sour ces) register use direct assignment operators and explicitly do not use the bit- wise operators (such as and or or). for exam - ple, "rstsrc = 0x02" is correct, but "rstsrc |= 0x02" is incorrect. 6. make certain that all writes to the rstsrc regist e r explicitly set the porsf bit to a '1'. areas to check are initialization code which enables ot her reset sources, such as the missing clock detector or comparator, for example, and instru ctions which force a so ftware reset. a global search on "rstsrc" can quickly verify this. rev. 1.0 141 c8051f360/1/2/3/4/5/6/7/8/9 13.3.2. 16.4.2 pswe maintenance 7. reduce the number of places in code where the pswe bit (b0 in psctl) is set to a '1'. there should be exactly one routine in code that sets pswe to a '1' to write flash bytes and one rou - tine in code that sets both pswe and psee both to a '1' to erase flash pages. 8. minimize the number of variable accesses while pswe is set to a '1'. handle pointer address updates and loop maintenance outside the "pswe = 1; ... pswe = 0;" area. code examples showing this can be found in an201, "writing to flash from firmware", available from the sili - con laboratories web site. 9. disable interrupts prior to setti ng pswe to a '1' and leave them disabled until after pswe has been reset to '0'. any interrup ts posted during the flash writ e or erase operation will be ser - viced in priority order after the flash operation has been completed and interrupts have been r e-enabled by software. 10. make certain that the flash write and erase pointer variables are not located in xram. see you r compiler documentation for instructions regard ing how to explicitly lo cate variables in dif - ferent memory areas. 11. add address bounds checking to the routines th at write or erase flash memory to ensure that a routine called with an illegal address does not re sult in modification of the flash. 13.3.3. system clock 12. if operating from an external crystal, be advised that crystal performance is susceptible to electrical interference and is sensitive to layout and to changes in temperature. if the system is operating in an electrically noi sy environment, use the internal oscillator or use an external cmos clock. 13. if operating from the ex ternal osc illator, switch to the internal oscillator during flash write or erase operations. the external oscillator can continue to run, and the cpu can switch back to the external oscillator after th e flash operation has completed. c8051f360/1/2/3/4/5/6/7/8/9 142 rev. 1.0 sfr definition 13.1. bits 7?2: unused. read = 000000b, write = don't care. bit 1: psee: program store erase enable. setting this bit allows an entire page of th e flash program memory to be erased provided the pswe bit is also set. afte r setting this bit, a write to flash memory using the movx instruction will erase the entire page that contains the loca tion addressed by the movx instruction. the value of the data byte written does not matter. note: the flash page con- taining the read lock byte and write/erase lock byte cannot be erased by software. 0: flash program memory erasure disabled. 1: flash program memory erasure enabled. bit 0: pswe: program store write enable. setting this bit allows writing a byte of dat a to the flash program memory using the movx write instruction. the location must be erased prior to writing data. 0: write to flash program memory disabled. movx write operations target external ram. 1: write to flash program memory enabled. movx write operations target flash memory. sfr page: sfr address: 0 0x8f r/w r/w r/w r/w r/w r/w r/w r/w reset value ? ? ? ? ? ? psee pswe 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 psctl: program store read/write control sfr definition 13.2. flkey: flash lock and key bits 7?0: flkey: flash lock and key register write: this register provides a lock and key function for flash erasures and writes. flash writes and erases are enabled by writing 0xa5 fo llowed by 0xf1 to th e flkey register. flash writes and erases are aut omatically disabled after the next write or erase is complete. if any writes to flkey are performed inco rrectly, or if a flash write or erase ope ration is attempted while these operations are dis abled, the flash will be permanently locked fr om writes or era- sures until the next device reset. if an applicat ion never writes to flash, it can intentionally lock the flash by writing a non-0xa5 value to flkey from software. read: when read, bits 1-0 indicate the current flash lock state. 00: flash is write/erase locked. 01: the first key code has been written (0xa5). 10: flash is unlocked (w rites/erases allowed). 11: flash writes/erases disa bled until the next reset. sfr page: sfr address: 0 0xb7 r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rev. 1.0 143 c8051f360/1/2/3/4/5/6/7/8/9 13.4. flash read timing on reset, the c8051f36x flash read timing is conf igured for operation with system clocks up to 25 mhz. if the s ystem clock will not be increased above 25 mhz, then the flash timing r egister s may be left at their reset value. for every flash read or fetch, the system provides an inter nal flash read strobe to the flash memory. the flash read strobe lasts for one or two system clock cycles, based on the flrt bits (flscl.4 and flscl.5). if the system clock is greater than 25 mhz, the flrt bit must be changed to the appropri - ate setting. otherwise, data read or fetched from flash ma y not represent the actual contents of flash. when the flash read strobe is asserted, flash memory is active. when it is de-asserted, flash memory is in a low power state. the recommended procedure for updating flrt is: step 1. select sysclk to 25 mhz or less. s tep 2. disable the prefetch engine (chpfen = ?0? in cch0cn register). step 3. set the flrt bits to th e appropriate setting for the sysclk. step 4. enable the pref etch engine (chpfen = ?1? in cch0cn register). sfr definition 13.3. bits 7?6: unused. read = 00b. write = don?t care. bits 5?4: flrt: flash read time. these bits should be programmed to the smalle st allowed value, according to the system clock speed. 00: sysclk < 25 mhz. 01: sysclk < 50 mhz. 10: sysclk < 75 mhz. 11: sysclk < 100 mhz. bits 3?0: reserved. read = 0 000b. must write 0000b. important note: when changing the flrt bits to a lower setting (e.g. when changing from a value of 11b to 00b), cache reads, cache writes, and the prefetch engine should be disabled using the cch0cn regi ster (see sfr definition 14.1). sfr page: sfr address: 0 0xb6 r/w r/w r/w r/w r/w r/w r/w r/w reset value ? ? flrt reserved reserved reserved reserved 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 flscl: flash memory control table 13.2. flash electrical characteristics v dd = 2.7 to 3.6 v; ?40 to +85 c. endurance erase cycle time write cycle time *note: 1024 bytes at location 0x7c00 to 0x7fff are reserved. c8051f360/1/2/3/4/5/6/7/8/9 144 rev. 1.0 parameter conditions min typ max units flash size c8051f360/1/2/3/4/5/6/7 32768* bytes c8051f368/9 16384 20 k 250 k erase/write 81012 ms 37 47 57 s rev. 1.0 145 c8051f360/1/2/3/4/5/6/7/8/9 14. branch target cache the c8051f36x device fam ilies incorporate a 32x4 byte branch target cache with a 4-byte prefetch e ngine. because the access time of the flash memory is 40 ns, and the minimum instruction time is 10 ns (c 8051f360/1/2/3/4/5/6/7) or 20 ns (c8051f368/9), the branch target cache and prefetch engine are nec - essary for full-speed code execution. instructions are read from flash memory four bytes at a time by the p refetch engine, and given to the cip-51 processor co re to execute. when running linear code (code with - out any jumps or branches), the prefetch engine alone allows instructions to be executed at full speed. when a code branch occurs, a search is performe d for the branch target (destination address) in the cache. if the branch target information is found in th e cache (called a ?cache hit?), the instruction data is read from the cache and immediately returned to the cip-51 with no delay in code execution. if the branch target is not found in the cache (called a ?cache miss?), the processor may be stalled for up to four clock cycles while the next set of four instructions is retrieved from flash memory. each time a cache miss occurs, the requested instruction data is written to the cache if allowed by the current cache settings. a data flow diagram of the interaction between the cip-51 and the branch target cache and prefetch engine is shown in figure 14.1 . flash memory branch target cache prefetch engine instruction data cip-51 instruction address figure 14.1. branch ta rget cache data flow 14.1. cache and prefetch operation the branch target cache maintains two sets of memory locations: ?slots? and ?tags?. a slot is where the cached instruction data from flash is stored. each sl ot holds four consecutive code bytes. a tag contains the 13 most significant bits of the corresponding fl ash address for each four-b yte slot. thus, instruction data is always cached along four-byte boundaries in code space. a tag also contains a ?valid bit?, which indicates whether a cache location contains valid inst ruction data. a special cach e location (called the lin - ear tag and slot), is reserved fo r use by the pr efetch engine. the cache organization is shown in figure 14.2 . each time a flash read is requested, the address is compared with all valid cache tag loca - tions (including the linear tag). if any of the tag loca tion s match the requested address, the data from that slot is immediately provided to t he cip-51. if the requested address ma tches a location that is currently being read by the prefetch engine, the cip-51 will be stalled until the re ad is complete. if a match is not found, the current prefetch operation is abandoned, and a new prefetch operation is initiated for the requested instruction data. when the prefetch oper ation is finished, the cip-51 begins executing the instructions that were retrieved, and the prefetch engine begins reading the next four-byte word from flash memory. if the newly-fe tched data also meets the cr iteria necessary to be cached , it will be written to the cache in the slot indicated by the current replacement algorithm. c8051f360/1/2/3/4/5/6/7/8/9 146 rev. 1.0 the replacement algorithm is selected with th e cache algorithm bit, cha lgm (cch0tn.3). when chalgm is cleared to ?0?, the cache will use the re bound algorithm to replace cache locations. the rebound algorithm replaces locations in order from the beginning of cache memory to the end, and then from the end of cache memory to the beginning. when chalgm is set to ?1?, the cache will use the pseudo-random algorithm to replace cache locations. the pseudo-random algorithm uses a pseudo-ran - dom number to determine which cache location to repl ace. the cache can be manually emptied by writing a ?1? to the chflush bit (cch0cn.4). slot = 4 instruction data bytes 0 0 tag 27 slot 27 v27 tag 31 slot 31 v31 tag 30 slot 30 v30 tag 2 slot 2 v2 tag 1 slot 1 v1 tag 0 slot 0 v0 tag 29 slot 29 v29 tag 28 slot 28 v28 linear tag linear slot vl prefetch data valid bit address data cache data tag = 13 msbs of absolute flash address a14 a2 a1 a0 1 0 0 1 1 1 byte 0 byte 1 byte 2 byte 3 figure 14.2. branch target cache organization 14.2. cache and prefetch optimization by default, the branch target cache is configured to provide code speed improvements for a broad range of circumstances. in most applications, the cache control registers should be left in their reset states. sometimes it is desirable to optimize the execution time of a specific routine or critical timing loop. the branch target cache includes options to exclude caching of certain type s of data, as well as the ability to pre-load and lock time-critical branch lo cations to optimize execution speed. the most basic level of cache cont r ol is implemented with the cache miss penalty threshold bits, chm - sth (cch0tn.1?0). if the processor is stalled during a pr efetch operation for more clock cycles than the number stored in chmsth, the requested data will be cached when it becomes available. the chmsth bits are set to zero by default, mean ing that any time the processor is st alled, the new data will be cached. if, for example, chmsth is equal to 2, any cache miss causing a delay of 3 or 4 clock cycles will be cached, while a cache miss causing a dela y of 1?2 clock cycles will not be cached. rev. 1.0 147 c8051f360/1/2/3/4/5/6/7/8/9 certain types of instruction data or certain blocks of code can also be excluded from caching. the destina - tions of reti instructions are, by de fault, excluded from caching. to enable caching of reti destinations, the chreti bit (cch0cn.3) can be set to ?1?. it is generally not beneficial to cache reti destinations unless the same instruction is likely to be interrupted repeatedly (such as a code loop that is waiting for an interrupt to happen). instructions th at are part of an interrupt service routine (isr) can also be excluded from caching. by default, isr instructions are cached, but this can be disabled by clearing the chisr bit (cch0cn.2) to ?0?. the other inform ation that can be explicitly excluded from caching are the data returned by movc instructions. cle aring the chmov bit (cch0cn.1) to ?0? will disable caching of movc data. if movc caching is allowed, it can be restrict ed to only use slot 0 for the movc information (exclud - ing cache push operations). the chfixm bit (cch0tn.2) controls this behavior. further cache control can be implemented by disabling all c ache writes. cache writ es can be disabled by clearing the chwren bit (cch0cn.7) to ?0?. although normal cache writes (such as those after a cache miss) are disabled, data can still be written to the cache with a cach e push operation. disabling cache writes can be used to prevent a non-critical section of code from changing the cache contents. note that regardless of the value of chwren, a flash write or erase operation au tomatically removes the affected bytes from the cache. cache reads and the prefetch engine can also be individually disabled. disabling cache reads forces all instructions data to execute from flash memory or from the prefetch engine. to dis - able cache reads, the chrden bit (cch0cn.6) can be cleared to ?0?. note that when cache reads are dis - abled, cache writes will still occur (if chwren is set to ?1?). disabling the prefetch engine is accomplished using the chpfen bit (cch0cn.5). when this bit is clea red to ?0?, the prefetch engine will be disabled. if both chpfen and chrden are ?0?, code will execute at a fixed rate, as instruct ions become available from the flash memory. cache locations can also be pre-loaded and locked with time-critical branch destinations. for example, in a system with an isr that must respond as fast as po ssible, the entry point for the isr can be locked into a cache location to minimize the re sponse latency of the isr. up to 30 locations can be locked into the cache at one time. instructions are locked into cache by enabling cache push operations with the chpush bit (cch0lc.7). when chpush is set to ?1?, a movc instruction will cause the four-byte segment contain - ing the data byte to be written to the cache slot location indicated by chslo t (c ch0lc.4-0). chslot is them decremented to point to the next lockable cache location. this process is called a cache push opera - tion. cache locations that are abov e chslot ar e ?locked?, and cannot be changed by the processor core, as shown in figure 14.3 . cache locations can be unlocked by using a cache pop operation. a cache pop is performed by writing a ?1? to the chpop bit (cch0lc.6) . when a cache pop is initiated, the value of chslot is incremented. this unlocks the most recently locked cache location, but does not remove the information from the cache. note that a cache pop should not be initiated if chslot is equal to 11110b. doing so may have an adverse effect on cache performance. important: although locking cache loca - tion 1 is not explicitly disabled by hardware, the entire cache will be unlocked when chslot is e qual to 00000b. therefore, cache locations 1 and 0 must remain unlocked at all times. tag 31 slot 31 tag 30 slot 30 tag 2 slot 2 tag 1 slot 1 tag 0 slot 0 tag 29 slot 29 tag 28 slot 28 chslot = 27 locked locked locked unlocked unlocked unlocked lock status cache push operations decrement chslot cache pop operations increment chslot locked tag 27 slot 27 unlocked unlocked tag 26 slot 26 unlocked c8051f360/1/2/3/4/5/6/7/8/9 148 rev. 1.0 figure 14.3. cache lock operation rev. 1.0 149 c8051f360/1/2/3/4/5/6/7/8/9 sfr definition 14.1. cch0cn: cache control bit 7: chwren: cache write enable. this bit enables the processor to write to the cache memory. 0: cache contents are not allowed to change, except during flash writes/erasures or cache locks. 1: writes to cache memory are allowed. bit 6: chrden: cach e read enable. this bit enables the processor to read instructions from the cache memory. 0: all instruction data comes from flash memory or the prefetch engine. 1: instruction data is obtained from cache (when available). bit 5: chpfen: cache prefetch enable. this bit enables the prefetch engine. 0: prefetch engine is disabled. 1: prefetch engine is enabled. bit 4: chflsh: cache flush. when written to a ?1?, this bit clears the cache contents. this bit always reads ?0?. bit 3: chreti: cache reti destination enable. this bit enables the destination of a reti address to be cached. 0: destinations of reti instructions will not be cached. 1: reti destinatio ns will be cached. bit 2: chisr: cache isr enable. this bit allows instructions wh ich are part of an interrupt service routine (isr) to be cached. 0: instructions in isrs will no t be loaded into cache memory. 1: instructions in isrs can be cached. bit 1: chmovc: cache movc enable. this bit allows data requested by a movc instruction to be loaded into the cache memory. 0: data requested by movc instructions will not be cached. 1: data requested by movc instruct ions will be loaded into cache memory. bit 0: chblkw: block write enable. this bit allows block writes to flash memory from software. 0: each byte of a software fl ash write is written individually. 1: flash bytes are written in groups of four (for code space writes). sfr page: sfr address: f 0x84 r/w r/w r/w r/w r/w r/w r/w r/w reset value chwren chrden chpfen chflsh chreti chisr chmovc chblkw 11100110 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 c8051f360/1/2/3/4/5/6/7/8/9 150 rev. 1.0 sfr definition 14.2. cch0tn: cache tuning bits 7?4: chmsctl: cache miss pe nalty accumulator (bits 4?1). these are bits 4-1 of the cache miss penalty accu mulator. to read these bits, they must first be latched by reading the chmscth bits in the cch0ma register (see sfr definition 14.4). bit 3: chalgm: cache algorithm select. this bit selects the cache replacement algorithm. 0: cache uses rebound algorithm. 1: cache uses pseudo-random algorithm. bit 2: chfixm: cache fix movc enable. this bit forces movc writes to the cache memory to use slot 0. 0: movc data is written according to the current algorithm selected by the chalgm bit. 1: movc data is always written to cache slot 0. bits 1?0: chmsth: cache miss penalty threshold. these bits determine w hen missed instruction data will be cached. if data takes longer than chmsth cl ocks to obtain, it will be cached. sfr page: sfr address: f 0xc9 r/w r/w r/w r/w r/w r/w r/w r/w reset value chmsctl chalgm chfixm chmsth 00000100 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rev. 1.0 151 c8051f360/1/2/3/4/5/6/7/8/9 sfr definition 14.3. cch0lc: cache lock control bit 7: chpush: cache push enable. this bit enables cache push o perations, which will lock information in cache slots using movc instructions. 0: cache push operations are disabled. 1: cache push operations are enabled. when a movc read is exec uted, the requested 4- byte segment containing the data is locked into the cache at the location indicated by chslot, and chslot is decremented. note: no more than 30 cache slots should be locked at one time, since the entire cache will be unlocked when chslot is equal to 0. bit 6: chpop: cache pop. writing a ?1? to this bit will in crement chslot and then unlock t hat location. this bit always reads ?0?. note that cache pop operations should not be performed while chslot = 11110b. ?pop?ing more cache slots than have been ?push?ed will have indeterminate results on the cache performance. bit 5: reserved. read = 0b. must write 0b. bits 4?0: chslot: cache slot pointer. these read-only bits are the pointer into the cache lock stack. locations above chslot are locked, and will not be change d by the processor, exc ept when chslot equals 0. sfr page: sfr address: f 0xd2 r / wr / wr rrrrrr e s e t v a l u e chpush chpop reserved chslot 00011111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 c8051f360/1/2/3/4/5/6/7/8/9 152 rev. 1.0 sfr definition 14.4. cch0ma: cache miss accumulator bit 7: chmsov: cache miss penalty overflow. this bit indicates when the cache miss pena lty accumulator has overflowed since it was last written. 0: the cache miss penalty accumulator has not overflowed since it was last written. 1: an overflow of the cache miss penalty accumulator has occurred since it was last written. bits 6?0: chmscth: cache miss pe nalty accumulator (bits 11?5) these are bits 11-5 of the cach e miss penalty accumulator. the next four bits (bits 4-1) are stored in chmsctl in the cch0tn register. the cache miss penalty accumulator is increment ed every clock cycle that the processor is delayed due to a cache miss. this is primarily used as a diagnostic feat ure, when optimizing code for execution speed. writing to chmscth clears the lower 5 bits of the cache miss penalty accumulator. reading from chmscth returns the current value of chmstch, and latches bits 4-1 into chmstcl so that they can be read. because bit 0 of the cache miss penalty accumulator is not available, the cumulative miss pe nalty is equal to 2 * (cchmstch:cchmstcl). sfr page: sfr address: f 0xd3 r r/w r/w r/w r/w r/w r/w r/w reset value chmsov chmscth 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr definition 14.5. flstat: flash status bit 7?1: reserved. read = 0000 000b. must write 0000000b. bit 0: flbusy: flash busy this bit indicates when a flash write or erase operation is in progress. 0: flash is idle or reading. 1: flash write/erase operation is currently in progress. sfr page: sfr address: f 0xac r r/w r/w r/w r/w r/w r/w r/w reset value reserved reserved reserved reserved reserved reserved reserved flbusy 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rev. 1.0 153 c8051f360/1/2/3/4/5/6/7/8/9 15. external data memory interface and on-chip xram for c8051f36x devices, 1k bytes of ram are included on-chip and mapped into the external data memory space (xram). additionally, an external memory in terface (emif) is available on the c8051f360/3 devices, which can be used to access off-chip data memories and memory-mapped devices connected to the gpio ports. the external memory space may be accessed using the external move instruction (movx) and the data pointer (dptr), or using the mo vx indirect addressing mode using r0 or r1. if the movx instruction is used with an 8-bit address opera nd (such as @r1), then the high byte of the 16-bit address is provided by the external memory interface control regist er (emi0cn, shown in sfr definition 15.1 ). note: the movx instruction can also be used for writing to the flash memory. see section ?13. flash memory? on page 135 for details. the movx instruction accesses xram by default. 15.1. accessing xram the xram memory space is accessed using the mo vx instruction. the movx instruction has two forms, both of which use an indirect addressing method. the first method uses the data pointer, dptr, a 16-bit register which contains the effective address of the xram location to be read from or written to. the sec - ond method uses r0 or r1 in combination with the emi0 cn register to generate the effective xram address. examples of both of these methods are given below. 15.1.1. 16-bit movx example the 16-bit form of the movx instructi on accesses the memory location po inted to by the contents of the dptr register. the following series of instructions reads the value of the byte at address 0x1234 into the accumulator a: mov dptr, #1234h ; load dptr with 16-bit address to read (0x1234) movx a, @dptr ; load contents of 0x1234 into accumulator a the above example uses the 16-bit immediate mov inst ru ction to set the contents of dptr. alternately, the dptr can be accessed through the sfr registers dph, which contains the upper 8-bits of dptr, and dpl, which contains the lower 8-bits of dptr. 15.1.2. 8-bit movx example the 8-bit form of the movx instruction uses the content s of the emi0cn sfr to determine the upper 8-bits of the effective address to be accessed and the contents of r0 or r1 to determine the lower 8-bits of the effective address to be accessed. the following series of instructions read the contents of the byte at address 0x1234 into the accumulator a. mov emi0cn, #12h ; load high byte of address into emi0cn mov r0, #34h ; load low byte of address into r0 (or r1) movx a, @r0 ; load contents of 0x1234 into accumulator a c8051f360/1/2/3/4/5/6/7/8/9 154 rev. 1.0 15.2. configuring the external memory interface configuring the external memory interface consists of five steps: 1. configure the output modes of the associated po rt pins as either push-pull or open-drain (push-pull is most common), and skip the associated pins in the crossbar. 2. configure port latches to ?park? the emif pins in a dormant state (usually by setting them to logic ?1?). 3. select multiplexed mode o r non-multiplexed mode. 4. select the memory mode (on-chip only, split mode without bank select, split mode with bank selec t, or off-chip only). 5. set up timing to interface with off-chip memory or peripherals. each of these five steps is explained in detail in the following s ections. the po rt selection, multiplexed mode selection, and mode bits are located in the emi0cf register shown in sfr definition 15.2 . 15.3. port configuration the external memory interface appears on ports 1, 2 (non-multiplexed mode only), 3, and 4 when it is used for off-chip memory access. when the emif is used in multiplexed mode, the crossbar should be configured to skip over the ale control line (p0.0) using the p0skip register. the other control lines, /rd (p4.4) and /wr (p4.5), are not available on the crossbar and do not need to be skipped. for more infor - mation about configuring the crossbar, see section ?17.3. general purpose port i/o? on page 190 . the emif pinout is shown in ta b l e 15.1 on page 155 . the external memory interface claims the associated po rt pins for memory oper ations only during the execution of an off-chip movx instruction. once the movx instruction has completed, control of the port pins reverts to the port latches or to the crossbar settings for those pins. see section ?17. port input/out - put? on page 183 for more information about the crossbar a nd port operation and configuration. the port latches should be explicitly configured to ?park? the external memory interface pins in a dormant s tate, most commonly by setting them to a logic ?1? . during the execution of the movx instruc tion, the external memory inte rface will explicitly disable the driv - ers on all port pins that are acting as inputs (data[ 7:0] dur ing a read operation , for example). the output mode of the port pins (whether the pin is configured as open-drain or push-pull) is unaffected by the external memory interface operation, and remains cont rolled by the pnmdout registers. in most cases, the output modes of all emif pins should be configured for push-pull mode. table 15.1. emif pinout (c8051f360/3) rev. 1.0 155 c8051f360/1/2/3/4/5/6/7/8/9 sfr definition 15.1. emi0cn: external memo ry interface control bits 7?0: pgsel[7:0]: xr am page select bits. the xram page select bits provide the high byte of the 16-bit external data memory address when using an 8-bit movx command, effectively selecting a 256-byte page of ram. 0x00: 0x0000 to 0x00ff 0x01: 0x0100 to 0x01ff ... 0xfe: 0xfe00 to 0xfeff 0xff: 0xff00 to 0xffff sfr page: sfr address: all pages 0xaa r/w r/w r/w r/w r/w r/w r/w r/w reset value pgsel7 pgsel6 pgsel5 pgsel4 pgsel 3 pgsel2 pgsel1 pgsel0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 multiplexed mode non multiplexed mode signal name port pin signal name port pin /rd p4.4 /rd p4.4 /wr p4.5 /wr p4.5 ale p0.0 ale p0.0 d0/a0 p1.0 d0 p1.0 d1/a1 p1.1 d1 p1.1 d2/a2 p1.2 d2 p1.2 d3/a3 p1.3 d3 p1.3 d4/a4 p1.4 d4 p1.4 d5/a5 p1.5 d5 p1.5 d6/a6 p1.6 d6 p1.6 d7/a7 p1.7 d7 p1.7 a8 p3.4 a0 p2.0 a9 p3.5 a1 p2.1 a10 p3.6 a2 p2.2 a11 p3.7 a3 p2.3 a12 p4.0 a4 p2.4 a13 p4.1 a5 p2.5 a14 p4.2 a6 p2.6 a15 p4.3 a7 p2.7 ? ? a8 p3.4 ? ? a9 p3.5 ??a 1 0p 3 . 6 ??a 1 1p 3 . 7 ??a 1 2p 4 . 0 ??a 1 3p 4 . 1 ??a 1 4p 4 . 2 ??a 1 5p 4 . 3 c8051f360/1/2/3/4/5/6/7/8/9 156 rev. 1.0 sfr definition 15.2. emi0cf: external memory configuration bits 7?5: unused. read = 000b. write = don?t care. bit 4: emd2: emif multiplex mode select. 0: emif operates in multiplexed address/data mode. 1: emif operates in non-multiplexed mode (separate address and data pins). bits 3?2: emd1?0: emif operating mode select. these bits control the operating mode of the external memory interface. 00: internal only: movx accesses on-chip xr am only. all effective addresses alias to on-chip memory space. 01: split mode without bank select: accesses below the 1 k boundary are directed on-chip. accesses above the 1 k boundary are directed off-chip. 8-bit off-chip movx operations use the current contents of the address high port latches to resolve upper address byte. note that in order to access off-chip spac e, emi0cn must be set to a page that is not contained in the on-chip address space. 10: split mode with bank select: accesses below the 1 k boundary are directed on-chip. accesses above the 1 k boundary are directed off-chip. 8-bit off-chip movx operations use the contents of emi0cn to determine the high-byte of the address. 11: external only: movx accesses off-chip xram only. on-chip xram is not visible to the cpu. bits 1?0: eale1?0: ale pulse-width select bits (only has effect when emd2 = 0). 00: ale high and ale low pulse width = 1 sysclk cycle. 01: ale high and ale low pulse width = 2 sysclk cycles. 10: ale high and ale low pulse width = 3 sysclk cycles. 11: ale high and ale low pulse width = 4 sysclk cycles. sfr page: sfr address: f 0xc7 r/w r/w r/w r/w r/w r/w r/w r/w reset value ? ? ? emd2 emd1 emd0 eale1 eale0 00000011 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rev. 1.0 157 c8051f360/1/2/3/4/5/6/7/8/9 15.4. multiplexed and non-multiplexed selection the external memory interface is capable of acting in a multiplexe d mode or a non-multiplexed mode, depending on the state of the emd2 (emi0cf.4) bit. 15.4.1. multiplexed configuration in multiplexed mode, the data bus and the lower 8-bits of the address bus share the same port pins: ad[7:0]. in this mode , an external latch (74hc373 or equivalent logic gate) is used to hold the lower 8-bits of the ram address. the external latch is controlled by the ale (address latch enable) signal, which is driven by the external memory interface logic. an example of a multiplexed configuration is shown in figure 15.1 . in multiplexed mode, the external movx operation can b e broken into two phases delineated by the state of the ale signal. during the first phase, ale is high and the lower 8-bits of the address bus are pre - sented to ad[7:0]. during this phase , the address latch is configured such that the ?q? outputs reflect the states of the ?d? inputs. when ale falls, signaling th e beginning of the second phase, the address latch outputs remain fixed and are no longer dependent on the latch inputs. later in the second phase, the data bus controls the state of the ad[7:0] port at the time /rd or /wr is asserted. see section ?15.6.2. multiplexed mode? on page 165 for more information. address/data bus address bus e m i f a[15:8] ad[7:0] /wr /rd ale 64 k x 8 sram oe we i/o[7:0] 74hc373 g dq a[15:8] a[7:0] ce v dd 8 (optional) figure 15.1. multiplexed configuration example c8051f360/1/2/3/4/5/6/7/8/9 158 rev. 1.0 15.4.2. non-multiplexed configuration in non-multiplexed mode, the data bus and the address bus pins are not shared. an example of a non-multiplexed config uration is shown in figure 15.2 . see section ?15.6.1. non-multiplexed mode? on page 162 for more information about non-multiplexed operation. address bus e m i f a[15:0] 64 k x 8 sram a[15:0] data bus d[7:0] i/o[7:0] v dd 8 /wr /rd oe we ce (optional) figure 15.2. non-multiplexed configuration example rev. 1.0 159 c8051f360/1/2/3/4/5/6/7/8/9 15.5. memory mode selection the external data memory space can be configured in one of four modes, shown in figure 15.3, based on the emif mode bits in the emi0cf register ( sfr definition 15.2 ). these modes are summarized below. more information about the different modes can be found in section ?15.6. timing? on page 160 . emi0cf[3:2] = 00 0xffff 0x0000 emi0cf[3:2] = 11 0xffff 0x0000 emi0cf[3:2] = 01 0xffff 0x0000 emi0cf[3:2] = 10 on-chip xram on-chip xram on-chip xram on-chip xram on-chip xram on-chip xram off-chip memory (no bank select) on-chip xram 0xffff 0x0000 off-chip memory (bank select) on-chip xram off-chip memory figure 15.3. emif operating modes 15.5.1. internal xram only when emi0cf.[3:2] are set to ?00?, all movx instructions will ta rget the internal xram space on the device. memory accesses to addres ses beyond the populated space will wrap on 1k bound aries. as an example, the addresses 0x0400 and 0x1000 both evaluate to address 0x0000 in on-chip xram space. ? 8-bit movx operations use the contents of emi0cn to determine the high-byte of the effective address and r0 or r1 to determine the lo w-byte of the effective address. ? 16-bit movx operations use the contents of the 16 -bit dptr to determine the effective address. 15.5.2. split mode without bank select when emi0cf.[3:2] are set to ?01?, the xram memory map is split into two areas, on-chip space and off-chip space. ? effective addresses below the internal xram size boundary will access on-chip xram space. ? effective addresses above the internal xr am size boundary will ac cess off-chip space. ? 8-bit movx operations use the contents of emi0 cn to determine whether the memory access is on-chip or off-chip. however, in the ?no bank select? mode, an 8-bi t movx operation will not drive the upper 8-bits a[15:8] of the address bus during an off-chip access. this allows the user to manipulate the upper address bits at will by setting the port state directly via the port latc hes. this behavior is in contrast with ?split mode with bank select? described below. the lower 8-bits of the address bus a[7:0] are driven, determined by r0 or r1. ? 16-bit movx operations use the contents of dp t r to determine whether the memory access is on-chip or off-chip, and unlike 8-bit movx operations, the full 16-bits of the address bus a[15:0] are driven during the off-chip transaction. c8051f360/1/2/3/4/5/6/7/8/9 160 rev. 1.0 15.5.3. split mode with bank select when emi0cf.[3:2] are set to ?10?, the xram memory map is split into two areas, on-chip space and off-chip space. ? effective addresses below the internal xram size boundary will access on-chip xram space. ? effective addresses above the internal xr am size boundary will ac cess off-chip space. ? 8-bit movx operations use the contents of emi0 cn to determine whether the memory access is on-chip or off-chip. the upper 8-bits of the addr ess bus a[15:8] are determined by emi0cn, and the lower 8-bits of the address bus a[7:0] are determined by r0 or r1. all 16-bits of the address bus a[15:0] are driven in ?bank select? mode. ? 16-bit movx operations use the contents of dp t r to determine whether the memory access is on-chip or off-chip, and the full 16-bits of the address bus a[15:0] are driven during the off-chip trans - action. 15.5.4. external only when emi0cf[3:2] are set to ?11?, all movx operations are directed to off-chip space. on-chip xram is not visible to the cpu. this mode is useful for ac cessing off-chip memory located between 0x0000 and the internal xram size boundary. ? 8-bit movx operations ignore the contents of emi0 cn. th e upper address bits a[15:8] are not driven (identical behavior to an off-chip access in ?split mode without bank select? described above). this allows the user to manipulate the upp er address bits at will by setting the port state directly. the lower 8-bits of the effective address a[7:0] are determined by the contents of r0 or r1. ? 16-bit movx operations use the contents of dptr to determine the effective address a[15:0]. the full 16 -bits of the address bus a[15:0] are driven during the off-chip transaction. 15.6. timing the timing parameters of the external memory inte rface can be configured to enable connection to devices having different setup and hold time requirements. the address setup time, address hold time, / rd and /wr strobe widths, and in multiplexed mode, the width of the ale pulse are all programmable in units of sysclk periods th rough emi0tc, shown in sfr definition 15.3 , and emi0cf[1:0]. the timing for an off-chip movx instruction can be calculate d by adding 4 sysclk cycles to the timing parameters defined by the emi0tc register. assumi ng non-multiplexed operation, the minimum execution time for an off-chip xram operat ion is 5 sysclk cycles (1 sysclk for /rd or /wr pulse + 4 sysclks). for multiplexed oper ations, the address latch enable signal will require a minimum of 2 additional sysclk cycles. therefore, the minimum execution time for an off-chip xram operation in multiplexed mode is 7 sysclk cycles (2 for /ale + 1 for /rd or /wr + 4) . the programmable setup and hold times default to the maximum delay settings after a reset. ta b l e 15.2 lists the ac parameters for the external memory interface, and figure 15.4 through figure 15.9 show the timing diagrams for the different external memory interface modes and movx operations. rev. 1.0 161 c8051f360/1/2/3/4/5/6/7/8/9 sfr definition 15.3. emi0tc: external me mory t iming control bits 7?6: eas1?0: emif address setup time bits. 00: address setup time = 0 sysclk cycles. 01: address setup time = 1 sysclk cycle. 10: address setup time = 2 sysclk cycles. 11: address setup time = 3 sysclk cycles. bits 5?2: ewr3?0: emif /wr and /rd pulse-width control bits. 0000: /wr and /rd pulse width = 1 sysclk cycle. 0001: /wr and /rd pulse width = 2 sysclk cycles. 0010: /wr and /rd pulse width = 3 sysclk cycles. 0011: /wr and /rd pulse width = 4 sysclk cycles. 0100: /wr and /rd pulse width = 5 sysclk cycles. 0101: /wr and /rd pulse width = 6 sysclk cycles. 0110: /wr and /rd pulse width = 7 sysclk cycles. 0111: /wr and /rd pulse width = 8 sysclk cycles. 1000: /wr and /rd pulse width = 9 sysclk cycles. 1001: /wr and /rd pulse wid th = 10 sysclk cycles. 1010: /wr and /rd pulse width = 11 sysclk cycles. 1011: /wr and /rd pulse width = 12 sysclk cycles. 1100: /wr and /rd pulse width = 13 sysclk cycles. 1101: /wr and /rd pulse width = 14 sysclk cycles. 1110: /wr and /rd pulse width = 15 sysclk cycles. 1111: /wr and /rd pulse width = 16 sysclk cycles. bits 1?0: eah1?0: emif address hold time bits. 00: address hold time = 0 sysclk cycles. 01: address hold time = 1 sysclk cycle. 10: address hold time = 2 sysclk cycles. 11: address hold time = 3 sysclk cycles. sfr page: sfr address: f 0xf7 r/w r/w r/w r/w r/w r/w r/w r/w reset value eas1 eas0 erw3 ewr2 ewr1 ewr0 eah1 eah0 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 c8051f360/1/2/3/4/5/6/7/8/9 162 rev. 1.0 15.6.1. non-multiplexed mode 15.6.1.1.16-bit movx: emi0cf[4:2] = ?101?, ?110?, or ?111?. emif address (8 msbs) from dph emif address (8 lsbs) from dpl emif write data t ach t wdh t acw t acs t wds addr[15:8] addr[7:0] data[7:0] /wr /rd emif address (8 msbs) from dph emif address (8 lsbs) from dpl t ach t rdh t acw t acs t rds addr[15:8] addr[7:0] data[7:0] /rd /wr emif read data nonmuxed 16-bit write nonmuxed 16-bit read p3.4?p4.3 p2 p1 p3.4?p4.3 p2 p1 p4.5 p4.4 p4.5 p4.4 p3.4?p4.3 p2 p1 p4.5 p4.4 p4.5 p4.4 p1 p2 p3.4?p4.3 figure 15.4. non-multip lexed 16-bit movx timing rev. 1.0 163 c8051f360/1/2/3/4/5/6/7/8/9 15.6.1.2.8-bit movx without bank select: emi0cf[4:2] = ?101? or ?111?. emif address (8 lsbs) from r0 or r1 emif write data t ach t wdh t acw t acs t wds addr[15:8] addr[7:0] data[7:0] /wr /rd emif address (8 lsbs) from r0 or r1 t ach t rdh t acw t acs t rds addr[15:8] addr[7:0] data[7:0] /rd /wr emif read data nonmuxed 8-bit write without bank select nonmuxed 8-bit read without bank select p3.4-p4.3 p2 p1 p4.5 p4.4 p4.4 p4.5 p1 p2 p3.4-p4.3 p2 p1 p4.4 p4.5 p4.5 p4.4 p1 p2 figure 15.5. non-multip lexed 8-bit movx withou t bank select timing c8051f360/1/2/3/4/5/6/7/8/9 164 rev. 1.0 15.6.1.3.8-bit movx with bank select: emi0cf[4:2] = ?110?. emif address (8 msbs) from emi0cn emif address (8 lsbs) from r0 or r1 emif write data t ach t wdh t acw t acs t wds addr[15:8] addr[7:0] data[7:0] /wr /rd emif address (8 msbs) from emi0cn emif address (8 lsbs) from r0 or r1 t ach t rdh t acw t acs t rds addr[15:8] addr[7:0] data[7:0] /rd /wr emif read data nonmuxed 8-bit write with bank select nonmuxed 8-bit read with bank select p3.4?p4.3 p2 p1 p4.5 p4.4 p4.4 p4.5 p1 p2 p3.4?p4.3 p3.4?p4.3 p2 p1 p4.4 p4.5 p4.5 p4.4 p1 p2 p3.4?p4.3 figure 15.6. non-multip lexed 8-bit movx with bank select timing rev. 1.0 165 c8051f360/1/2/3/4/5/6/7/8/9 15.6.2. multiplexed mode 15.6.2.1.16-bit movx: emi0cf[4:2] = ?001 ?, ?010?, or ?011?. addr[15:8] ad[7:0] t ach t wdh t acw t acs t wds ale /wr /rd emif address (8 msbs) from dph emif write data emif address (8 lsbs) from dpl t aleh t alel addr[15:8] ad[7:0] t ach t acw t acs ale /rd /wr emif address (8 msbs) from dph emif address (8 lsbs) from dpl t aleh t alel t rdh t rds emif read data muxed 16-bit write muxed 16-bit read p3.4?p4.3 p1 p0.0 p4.5 p4.4 p4.4 p4.5 p0.0 p1 p3.4?p4.3 p3.4?p4.3 p1 p0.0 p4.4 p4.5 p4.5 p4.4 p0.0 p1 p3.4?p4.3 figure 15.7. multiple xed 16-bit movx timing c8051f360/1/2/3/4/5/6/7/8/9 166 rev. 1.0 15.6.2.2.8-bit movx without bank select: emi0cf[4:2] = ?001? or ?011?. addr[15:8] ad[7:0] t ach t wdh t acw t acs t wds ale /wr /rd emif write data emif address (8 lsbs) from r0 or r1 t aleh t alel addr[15:8] ad[7:0] t ach t acw t acs ale /rd /wr emif address (8 lsbs) from r0 or r1 t aleh t alel t rdh t rds emif read data muxed 8-bit write without bank select muxed 8-bit read without bank select p3.4?p4.3 p1 p0.0 p4.5 p4.4 p4.4 p4.5 p0.0 p1 p3.4?p4.3 p1 p0.0 p4.4 p4.5 p4.5 p4.4 p0.0 p1 figure 15.8. multiplexed 8-bit mo vx without bank select timing rev. 1.0 167 c8051f360/1/2/3/4/5/6/7/8/9 15.6.2.3.8-bit movx with bank select: emi0cf[4:2] = ?010?. addr[15:8] ad[7:0] t ach t wdh t acw t acs t wds ale /wr /rd emif address (8 msbs) from emi0cn emif write data emif address (8 lsbs) from r0 or r1 t aleh t alel addr[15:8] ad[7:0] t ach t acw t acs ale /rd /wr emif address (8 msbs) from emi0cn emif address (8 lsbs) from r0 or r1 t aleh t alel t rdh t rds emif read data muxed 8-bit write with bank select muxed 8-bit read with bank select p3.4?p4.3 p1 p0.0 p4.5 p4.4 p4.4 p4.5 p0.0 p1 p3.4?p4.3 p3.4?p4.3 p1 p0.0 p4.4 p4.5 p4.5 p4.4 p0.0 p1 p3.4?p4.3 figure 15.9. multiplexed 8-bit movx with bank select timing table 15.2. ac parameters for exte rnal memory interface parameter description min* max* units t acs address/control setup time 0 3 x t sysclk ns t acw address/control pulse width 1 x t sysclk 16 x t sysclk ns t ach address/control hold time 0 3 x t sysclk ns t aleh address latch enable high time 1 x t sysclk 4 x t sysclk ns t alel address latch enable low time 1 x t sysclk 4 x t sysclk ns t wds write data setup time 1 x t sysclk 19 x t sysclk ns t wdh write data hold time 0 3 x t sysclk ns t rds read data setup time 20 ns t rdh read data hold time 0 ns *note: t sysclk is equal to one period of the device system clock (sysclk). c8051f360/1/2/3/4/5/6/7/8/9 168 rev. 1.0 rev. 1.0 169 c8051f360/1/2/3/4/5/6/7/8/9 16. oscillators the c8051f36x devices include a pr ogrammable internal hi gh-frequency oscillator, a programma ble inter - nal low-frequency oscillator, and an ex ternal oscillator drive circuit. th e internal high-frequency oscillator can be enabled, disabled, and calibrated using t he oscicn and oscicl registers, as shown in figure 16.1 . the internal low-frequency oscillator can be enabled/disabled and calibrated us ing the osclcn register, as shown in sfr definition 16.3 . both internal oscillators of fer a selectab le post-scaling feature. the system clock ca n be sourced by the external oscillator circ uit, either internal oscillator, or the on-chip phase-locked loop (pll). the internal oscillator's elec trical specifications are given in ta b l e 16.1 on page 171 and table 16.2 on page 172 . calibrated internal oscillator en sysclk n oscicl xtal1 xtal2 000 001 pll 010 agnd av+ oscicn ioscen ifrdy suspend ifcn1 ifcn0 osc input circuit oscxcn xtlvld xoscmd2 xoscmd1 xoscmd0 xfcn2 xfcn1 xfcn0 option 1 osclcn osclen osclrdy osclf3 osclf2 osclf1 osclf0 oscld1 oscld0 osclf oscld 100 option 4 xtal2 option 2 vdd xtal2 option 3 xtal2 low frequency oscillator en n oscld osclf clksel clkdiv1 clkdiv0 clksl1 clksl0 clksl2 figure 16.1. oscillator diagram 16.1. programmable internal hi gh-f requency (h-f) oscillator all devices include a calibra ted internal high -frequency oscillator that defaults as the system clock after a system reset. the internal oscillator period can be adjusted via the oscicl register as defined by sfr definition 16.1 . oscicl is factory calib r ated to obtain a 24.5 mhz frequency. electrical specifications for the precisio n internal osc illator are given in table 16.1 on page 171 and ta b l e 16.2 on page 172 . note that the system clock may be derived from the programmed internal os cilla - tor divided by 1, 2, 4, or 8, as defined by the ifcn bi t s in register oscicn. the divide value defaults to 8 following a reset. c8051f360/1/2/3/4/5/6/7/8/9 170 rev. 1.0 16.1.1. internal oscillator suspend mode when software writes a logic ?1? to suspend (oscicn.5), the internal oscillator is suspended. if the sys - tem clock is derived from t he internal oscillator , the input clock to the peripheral or cip-51 will be stopped until one of the following events occur: ? port 0 match event. ? port 1 match event. ? port 2 match event. ?comparator 0 enabled and output is logic ?0?. ?comparator 1 enabled and output is logic ?0?. when one of the intern al os cillator awakening events occur, the internal oscillator, cip-51, and affected peripherals resume normal operation, regardless of whether the event also causes an interrupt. the cpu resumes execution at the instructio n following the write to suspend. note: before entering suspend mode, sysclk should be switched to run off of the inte rnal oscillator and not the pll. when the cpu wakes due to the awakening event, the pll must be reinitialized before switching back to it as the sysclk source. sfr definition 16.1. oscicl: internal oscillator calibration bits 7?0: oscicl: internal oscillator calibration register. this register calibrates the internal osc illator period. the reset value for os cicl defines the internal oscillator base frequency. the reset value is factory ca librated to gen erate an inter- nal oscillator freque ncy of 24.5 mhz. sfr page: sfr address: f 0xbf r/w r/w r/w r/w r/w r/w r/w r/w reset value variable bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 . rev. 1.0 171 c8051f360/1/2/3/4/5/6/7/8/9 sfr definition 16.2. oscicn: internal os cillator control bit 7: ioscen: internal oscillator enable bit. 0: internal oscillator disabled. 1: internal oscillator enabled. bit 6: ifrdy: internal oscilla tor frequency ready flag. 0: internal oscillator not ru nning at progra mmed frequency. 1: internal oscillator runni ng at programmed frequency. bits 5: suspend: internal os cillator suspend enable bit. setting this bit to logic ?1? places the internal oscillator in suspend mode. the internal oscillator resumes operation when one of the suspen d mode awakening events occur. bits 4?2: reserved. read = 000b. must write 000b. bits 1?0: ifcn1-0: internal oscillator frequency control bits. 00: internal oscillator is divided by 8. (default) 01: internal oscillator is divided by 4. 10: internal oscillator is divided by 2. 11: internal oscillator is divided by 1. sfr page: sfr address: f 0xb7 r/w r r/w r r/w r/w r/w r/w reset value ioscen ifrdy suspend reserved reser ved reserved ifcn1 ifcn0 11000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 table 16.1. internal high frequency oscillat or electrical characteristics ?40c to +85c unless otherwise specified. 16.2. programmable internal low -frequency (l-f) oscillator all c8051f36x devices incl ude a programmable lo w-frequency internal oscillator, which is calibrated to a nominal frequency of 80 khz. the low-frequency oscillator circuit in cludes a divider that can be changed to divide the clock by 1, 2, 4, or 8, using the oscld bits in the osclcn register (see sfr definition 16.3 ). additionally, the osclf bits (osclcn5:2) can be used to adjust the oscillator?s output frequency. parameter conditions min typ max units calibrated internal oscillator fr equency 24 24.5 25 mhz internal oscillator supply current (from v dd ) oscicn.7 = 1 ? 450 600 a power supply sensitivity constant temperature ? 0.12 ? %/v temperature sensitivity constant supply ? 60 ? ppm/c external clock frequency 0 ? 30 mhz t xch (external clock high time) 15 ? ? ns t xcl (external clock low time) 15 ? ? ns c8051f360/1/2/3/4/5/6/7/8/9 172 rev. 1.0 16.2.1. calibrating the internal l-f oscillator timers 2 and 3 include capture func tions that can be used to capture the oscillato r frequency, when run - ning from a known time base. when either timer 2 or timer 3 is configured for l- f oscillator capture mode, a falling edge (timer 2) or rising edge (timer 3) of the low-frequency osc illator ?s output will cause a capture event on the corresponding timer. as a capture event occurs, the current timer value (tmrnh:tmrnl) is copied into the timer reload re gisters (tmrnrlh:tmrnrll). by recording the differ - ence between two successive time r capture values, the lo w-frequency oscillator? s period can be calcu - lated. the osclf bits can then be adjusted to produce the desire d oscillator frequency. sfr definition 16.3. osclcn: internal l-f oscillator control bit 7: osclen: internal l-f oscillator enable. 0: internal l-f oscillator disabled. 1: internal l-f oscillator enabled. bit 6: osclrdy: internal l-f oscillator ready. 0: internal l-f oscillato r frequency not stabilized. 1: internal l-f oscilla tor frequency stabilized. bits 5?2: osclf[3:0]: internal l-f oscillator frequen cy control bits. fine-tune control bi ts for the internal l-f oscillator frequency. when set to 0000b, the l-f oscillator operates at its fastest setting. when se t to 1111b, the l-f o scillator operates at its slowest setting. bits 1?0: oscld[1:0]: internal l-f oscillator divider select. 00: divide by 8 selected. 01: divide by 4 selected. 10: divide by 2 selected. 11: divide by 1 selected. sfr page: sfr address: f 0xad r/w r r/w r/w r/w r/w r/w r/w reset value osclen osclrdy osclf3 osclf2 osclf1 osclf0 oscld1 oscld0 00vvvv00 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 table 16.2. internal low frequency oscill ator electrical characteristics ?40c to +85c unless otherwise specified. parameter conditions min typ max units oscillator frequency oscld = 11b 72 80 88 khz oscillator supply current (from v dd ) 25 c, v dd = 3.0 v, osclcn.7 = 1 ?5.510a power supply sensitivity con stant temperature ? 2.4 ? %/v temperature sensitivity constant supply ? 30 ? ppm/c rev. 1.0 173 c8051f360/1/2/3/4/5/6/7/8/9 16.3. external oscill ator drive circuit the external oscillator circuit may drive an external cr ystal, ceramic resona tor, capacitor, or rc network. a cmos clock may also provide a clock input. for a crys tal or ceramic resonator configuration, the crystal/ resonator must be wired across the xtal1 and xtal2 pins as shown in option 1 of figure 16.1 . a 10 m ? resistor also must be wired across the xtal1 and xt al2 pins for the crystal/resonator configuration. in rc, capacitor, or cmos clock configuration, the cloc k source should be wired to the xtal2 pin as shown in option 2, 3, or 4 of figure 16.1 . the type of external osc illator must be selected in the oscxcn register, and the frequency control bits (xfcn) must be selected appropriately (see sfr definition 16.5 ). important note on external oscillator usage: po rt pins must be configured when using the external oscillator circuit. when the external oscillator drive ci rcuit is enabled in crystal/resonator mode, port pins p0.5 and p0.6 (c8051f360/3) or p0.2 and p0.3 (c8051f361/2/4/5/6/7/8/9) are used as xtal1 and xtal2 respectively. when the external oscillator drive circuit is enabled in capacitor, rc, or cmos clock mode, port pin p0.6 (c8051f360/3) or p0.3 (c8051f361/2/4/5 /6/7/8/9) is used as xtal2. the port i/o crossbar should be configured to skip the port pins used by the oscillator circuit; see section ?17.1. priority crossbar decoder? on page 185 for crossbar configuration. additionally , when using the ex ternal oscillator circuit in crystal/resonator, capacitor, or rc mode, the associated port pins should be configured as ana log inputs . in cmos clock mode, the associated pin should be configured as a digital input . see section ?17.2. port i/o initialization? on page 187 for details on port input mode s election. 16.4. system clock selection the internal oscillator requires little start-up time, an d may be enabled and selected as the system clock in the same write to oscicn. external crystals and ce ramic resonators typically require a start-up time before they are settled and ready for use as the syste m clock. the crystal valid flag (xtlvld in register oscxcn) is set to ?1? by hardware when the external os cillator is settled. to avoid reading a false xtlvld, in crystal mode software should delay at least 1 ms between enabling the ex ternal oscillator and checking xtlvld. rc and c modes typically require no startup time. the pll also requires time to lock onto the desired frequency, and the pll lock flag (plllck in register pll0cn) is set to ?1? by hardware once the pll is locked on the correct frequency. the clksl1-0 bits in register cl k sel select which oscillator sour ce generates the system clock. clksl1-0 must be set to ?01? for the system clock to ru n from the external oscillator; however the external oscillator may still clock certain periphe rals, such as the timers and pca, when the internal oscillator or the pll is selected as the system clock. the system clock may be switched on-the-fly between the internal and external oscillators or the pl l, so long as the selected oscilla tor source is enabled and settled. c8051f360/1/2/3/4/5/6/7/8/9 174 rev. 1.0 sfr definition 16.4. clksel: system clock selection bits 7?6: reserved. read = 00b. must write 00b. bits 5?4: clkdiv1-0: output sysclk divide factor. these bits can be used to pre-divide sysclk befor e it is output to a port pin through the crossbar. 00: output will be sysclk. 01: output will be sysclk/2. 10: output will be sysclk/4. 11: output will be sysclk/8. see section ?17. port input/output? on page 183 for more details about routing this output to a port pin. bit 3: reserved. read = 0b. must write 0b. bits 2?0: clksl2?0: system clock source select bits. 000: sysclk derived from the high-frequency internal oscilla tor, and scaled as per the ifcn bits in oscicn. 001: sysclk derived from the external oscillator circuit. 010: sysclk derived from the low-frequency internal oscilla tor, and scaled as per the oscld bits in osclcn. 011: reserved. 100: sysclk derived from the pll. 101-11x: reserved. sfr page: sfr address: f 0x8f r/w r/w r/w r/w r/w r/w r/w r/w reset value reserved reserved clkdiv1 clkdiv0 re served clksl2 clksl 1 clksl0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rev. 1.0 175 c8051f360/1/2/3/4/5/6/7/8/9 sfr definition 16.5. oscxcn: external oscillator control bit 7: xtlvld: crystal oscillator valid flag. ( valid only when xoscmd = 11x. ) 0: crystal oscillator is unused or not yet stable. 1: crystal oscillator is running and stable. bits 6?4: xoscmd2?0: exte rnal oscillator mode bits. 00x: external oscillator circuit off. 010: external cmos clock mode. 011: external cmos clock mode with divide by 2 stage. 100: rc osc illator mode. 101: capacitor oscillator mode. 110: crystal oscillator mode. 111: crystal oscillator mode with divide by 2 stage. bit 3: reserved. read = 0b. write = don't care. bits 2?0: xfcn2?0: external osc illator frequency control bits. 000-111: see table below: crystal mode (circuit from figure 16.1, option 1; xoscmd = 11x) choose xfcn value to match crystal frequency. rc mode (circuit from figure 16.1, option 2; xoscmd = 10x) choose xfcn value to match frequency range: f = 1.23(10 3 )/(r * c) , where f = frequency of os cillation in mhz c = capacitor value in pf r = pullup resistor value in k ? c mode (circuit from figure 16.1 , option 3; xoscmd = 10x) choose k factor (kf) for the oscillation frequency desired: f = kf/(c * v dd ) , where f = frequency of os cillation in mhz c = capacitor value on xtal1, xtal2 pins in pf v dd = power supply on mcu in volts sfr page: sfr address: f 0xb6 r r/w r/w r/w r r/w r/w r/w reset value xtlvld xoscmd2 xoscmd1 xoscmd0 res erved xfcn2 xfcn1 xfcn0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 xfcn crystal (xoscmd = 11x) rc (xoscmd = 100) c (xoscmd = 101) 000 f 32 khz f 25 khz k factor = 0.87 001 32 khz < f 84 khz 25 khz < f 50 khz k factor = 2.6 010 84 khz < f 225 khz 50 khz < f 100 khz k factor = 7.7 011 225 khz < f 590 khz 100 khz < f 200 khz k factor = 22 100 590 khz < f 1.5 mhz 200 khz < f 400 khz k factor = 65 101 1.5 mhz < f 4 mhz 400 khz < f 800 khz k factor = 180 110 4 mhz < f 10 mhz 800 khz < f 1.6 mhz k factor = 664 111 10 mhz < f 30 mhz 1.6 mhz < f 3.2 mhz k factor = 1590 c8051f360/1/2/3/4/5/6/7/8/9 176 rev. 1.0 16.5. external crystal example if a crystal or ceramic resonator is used as an external oscillator source for the mcu, the circuit should be configured as shown in figure 16.1 , option 1. the external oscillato r frequency contro l value (xfcn) should be chosen from the crystal column of the table in sfr definition 16.5 (oscxcn register). for example, an 11.0592 mhz crystal requires an xfcn setting of 111b. when the crystal oscillator is enabled , the oscillator amplitude detection circuit requires a settle time to achieve proper bias. waiting at least 1 ms between enabling the oscillato r and checking the xtlvld bit will prevent a premature switch to the external oscillator as the system clock. switching to the external oscillator before the crystal oscilla tor has stabilized can result in unpredictable behavior. the recom - mended procedure is: step 1. force the xtal1 and xtal2 pins low by writing 0's to the port latch. s tep 2. configure xtal1 and xtal2 as analog inputs. step 3. enable the external oscillator. step 4. wait at least 1 ms. step 5. poll for xtlvld => '1'. step 6. switch the system cl ock to the external oscillator. note: t uning-fork crystals may requir e additional settling time before xtlvld returns a valid result. the capacitors shown in the external crystal configur atio n provide the load capacitance required by the crystal for correct oscillation. these capacitors are "in series" as seen by the crystal and "in parallel" with the stray capacitance of the xtal1 and xtal2 pins. note: th e load capacitance depends upon the crystal an d the manufacturer. please refer to the crystal data sheet when completing these calculations. for example, a tuning-fork crystal of 32.768 khz with a recommended load capacitance of 12.5 pf should us e the configuration shown in figure 16.1 , option 1. the total value of th e cap acitors and the stray capac - itance of the xtal pins should equal 25 pf. with a stray capacitance of 3 pf per pin, the 22 pf capacitors yield an equivalent capacitance of 12.5 pf across the crystal, as shown in figure 16.2 . 22 pf 22 pf 32.768 khz xtal1 xtal2 10 m ? figure 16.2. 32. 768 khz external crystal example important note on external crystals: crystal oscillator circuits are qui te sensitive to pcb layout. the crystal should be placed as close as possible to the xtal pins on the device. the traces should be as short as possible and shielded with ground plane fr om any other traces which could introduce noise or interference. rev. 1.0 177 c8051f360/1/2/3/4/5/6/7/8/9 16.6. external rc example if an rc network is used as an external oscillator so urce for the mcu, the circ uit should be configured as shown in figure 16.1 , option 2. the capacitor should be no greater than 100 pf; however for very small capacitors, the total capacitance may be dominated by parasitic capacitance in the pcb layout. to deter - mine the required external oscilla tor frequency control va lue (xfcn) in the oscxcn register, first select the rc network value to prod uce the desired frequency of oscilla tion. if the frequency desired is 100 khz, let r = 246 k? an d c = 50 pf: f = 1.23(10 3 )/rc = 1.23 (10 3 )/[246 x 50] = 0.1 mhz = 100 khz referring to the table in sfr defini tion 16.5, the required xfcn setting is 010b. programming xfcn to a higher setting in rc mode will improve frequenc y accuracy at a slightly increased external oscillator supply current. 16.7. external capacitor example if a capacitor is used as an external oscillator for t he mcu, the circuit should be configured as shown in figure 16.1 , option 3. the capacitor should be no greater than 100 pf; however for very small capacitors, the total capacitance may be dominated by parasiti c ca pacitance in the pcb layout. to determine the required external oscillato r frequency control value (xfcn) in th e oscxcn register, select the capaci - tor to be used and find the fr equenc y of oscillati on from the equations below. assume v dd = 3.0 v and f = 75 khz: f = kf / (c x v dd ) 0.075 mhz = kf / (c x 3.0) since the frequency of roughly 75 khz is desired, select the k factor from the table in sfr definition 16.5 as kf = 7.7: 0.075 mhz = 7.7 / (c x 3.0) c x 3.0 = 7.7 / 0.075 mhz c = 102.6 / 3.0 pf = 34.2 pf therefore, the xfcn value to use in this example is 010b. c8051f360/1/2/3/4/5/6/7/8/9 178 rev. 1.0 16.8. phase-locked loop (pll) a phase-locked-loop (pll) is included, which is used to multiply the internal osc illator or an external clock source to achieve higher cpu operating freque ncies. the pll circuitry is designed to produce an output frequency between 25 mhz and 100 mhz, from a divided reference frequency between 5 mhz and 30 mhz. a block diagram of the pll is shown in figure 16.3 . pll0div pllm4 pllm3 pllm2 pllm1 pllm0 pll0mul plln7 plln6 plln5 plln4 plln3 plln2 plln1 plln0 pll0cn plllck pllsrc pllen pllpwr pll0flt pllico1 pllico0 plllp3 plllp2 plllp1 plllp0 0 1 internal oscillator external oscillator phase / frequency detection loop filter current controlled oscillator pll clock output divided reference clock figure 16.3. pll block diagram 16.8.1. pll input clock and pre-divider the pll circuitry can derive its refere nce clock from either the internal oscillator or an external clock source. the pllsrc bit (pll0cn.2) controls which cl ock source is used for the reference clock (see sfr definition 16.6 ). if pllsrc is set to ?0?, the internal os cillator source is used . note that the internal oscilla - tor divide factor (as spec ified by bits ifcn1-0 in register oscicn) will also apply to this clock. when pllsrc is set to ?1?, an external oscillator source will be us ed. the external oscillato r should be active and settled before it is selected as a reference clock for the pll circuit. the reference clock is divided down prior to the pll circuit, according to the contents of the pllm4-0 bits in the pll pre-divider register (pll0div), shown in sfr definition 16.7 . 16.8.2. pll multiplication and output clock the pll circuitry will multiply the divided reference clock by the multiplication factor stored in the pll0mul register shown in sfr definition 16.8 . to accomplish this, it uses a feedback loop consisting of a phase/frequency detector, a loop f ilter , and a current-controlled oscillato r (ico). it is important to config - ure the loop filter and the ico for the correct frequency ranges. the plllp3?0 bits (pll0flt.3?0) should b e set according to the divided reference clock frequency. likewise, the pllico1?0 bits (pll0flt.5?4) should be set according to the desired output frequency range. sfr definition 16.9 describes the proper settings to use for the plllp3?0 and pllico1?0 bits. whe n the pll is locked and stable at the desired frequency, the plllck bit (pll0cn. 5) will be set to a ?1?. the result ing pll frequency will be set accord - ing to the equation: pll frequency reference frequency plln pllm --------------- = where ?reference frequency? is the selected source clock frequency, plln is the pll multiplier, and pllm is the pll pre-divider. rev. 1.0 179 c8051f360/1/2/3/4/5/6/7/8/9 16.8.3. powering on and initializing the pll to set up and use the pll as the system clock af ter power-up of the devic e, the following procedure should be implemented: step 1. ensure that the reference clock to be used (internal or external) is running and stable. s tep 2. set the pllsrc bit (pll0cn.2) to select the desired clock source for the pll. step 3. program the flash read timing bits, flrt (flscl.5?4) to the appropriate value for the new clock rate (see section ?13. flash memory? on page 135). step 4. enable power to the pll by setting pllpwr (pll0cn.0) to ?1?. step 5. program the pll0div register to prod uce the divided reference frequency to the pll. step 6. program the plllp3?0 bits (pll0flt.3?0) to the appropriate range for the divided reference frequency. step 7. program the pllico1?0 bits (pll0flt.5?4) to the appropriate range for the pll output frequency. step 8. program the pll0mul register to the desired clock multiplication factor. step 9. wait at least 5 s, to provide a fast frequency lock. step 10. enable the pll by setting pllen (pll0cn.1) to ?1?. step 11. poll plllck (pll0cn.4) un til it changes from ?0? to ?1?. step 12. switch the system clock source to the pll using the clksel register. if the pll characteristics need to be changed when the pll is already running, the following procedure sh ould be implemented: step 1. the system clock should first be switched to either the internal osc illator or an external clock source that is running and stable, using the clksel register. step 2. ensure that the reference clock to be used for the new pll setting (internal or external) is running and stable. step 3. set the pllsrc bit (pll0cn.2) to select the new clock source for the pll. step 4. if moving to a faster frequency, program the flash read timing bits, flrt (flscl.5?4) to the appropriate value for the new clock rate (see section ?13. flash memory? on page 135). step 5. disable the pll by setting pllen (pll0cn.1) to ?0?. step 6. program the pll0div register to prod uce the divided reference frequency to the pll. step 7. program the plllp3?0 bits (pll0flt.3?0) to the appropriate range for the divided reference frequency. step 8. program the pllico1-0 bits (pll0flt.5?4) to the appropriate range for the pll output frequency. step 9. program the pll0mul register to the desired clock multiplication factor. step 10. enable the pll by setting pllen (pll0cn.1) to ?1?. step 11. poll plllck (pll0cn.4) un til it changes from ?0? to ?1?. step 12. switch the system clock source to the pll using the clksel register. step 13. if moving to a slower frequency, program the flash read timing bits, flrt (flscl.5?4) to the appropriate value for the new clock rate (see section ?13. flash memory? on page 135). important note: cache reads, cache writes, and the prefetch engine should be disabled whenever the flrt bits are changed to a lower setting. c8051f360/1/2/3/4/5/6/7/8/9 180 rev. 1.0 to shut down the pll, the s ystem clock should be switched to the in ternal oscillator or a stable external clock source, using the cl ksel register. next, disabl e the pll by setting plle n (pll0cn.1) to ?0?. finally, the pll can be powered off, by setting pllpwr (pll0cn.0) to ?0?. note that the pllen and pll - pwr bits can be cleared at the same time. sfr definition 16.6. pll0cn: pll control bits 7?5: unused. read = 000b. write = don?t care. bit 4: plllck: pll lock flag. 0: pll frequency is not locked. 1: pll frequency is locked. bit 3: reserved. read = 0b. must write 0b. bit 2: pllsrc: pll reference clock source select bit. 0: pll reference clock sour ce is internal oscillator. 1: pll reference clock sour ce is external oscillator. bit 1: pllen: pll enable bit. 0: pll is held in reset. 1: pll is enabled. pllpwr must be ?1?. bit 0: pllpwr: pll power enable. 0: pll bias generator is de-activated. no static power is consumed. 1: pll bias generator is active. must be set for pll to operate. sfr page: sfr address: f 0xb3 r/w r/w r/w r r/w r/w r/w r/w reset value ? ? ? plllck reserved pllsrc pllen pllpwr 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr definition 16.7. pll0div: pll pre-divider bits 7?5: unused. read = 000b. write = don?t care. bits 4?0: pllm4?0: pll reference clock pre-divider. these bits select the pre-divide value of the p ll reference clock. when set to any non-zero value, the reference clock will be divided by the value in pllm 4?0. when set to ?00000b?, the reference clock will be divided by 32. sfr page: sfr address: f 0xa9 r/w r/w r/w r/w r/w r/w r/w r/w reset value ? ? ? pllm4 pllm3 pllm2 pllm1 pllm0 00000001 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rev. 1.0 181 c8051f360/1/2/3/4/5/6/7/8/9 sfr definition 16.8. pll0mul: pll clock scaler bits 7?0: plln7?0: pll multiplier. these bits select the multiplicat ion factor of the divided pll reference clock. when set to any non-zero value, the multip lication factor will be equal to th e value in plln7-0. when set to ?00000000b?, the multiplicat ion factor will be equal to 256. sfr page: sfr address: f 0xb1 r/w r/w r/w r/w r/w r/w r/w r/w reset value plln7 plln6 plln5 plln4 plln3 plln2 plln1 plln0 00000001 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr definition 16.9. pll0flt: pll filter bits 7?6: unused. read = 00b. write = don?t care. bits 5?4: pllico1-0: pll current-c ontrolled oscillator control bits. selection is based on the desired output frequency, according to the following table: bits 3?0: plllp3-0: pll loop filter control bits. selection is based on the divided pll refere nce clock, according to the following table: all other states of plllp3?0 are reserved. sfr page: sfr address: f 0xb2 r/w r/w r/w r/w r/w r/w r/w r/w reset value ? ? pllico1 pllico0 plllp3 plllp2 plllp1 plllp0 00110001 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 pll output clock pllico1-0 65?100 mhz 00 45?80 mhz 01 30?60 mhz 10 25?50 mhz 11 divided pll reference clock plllp3-0 19?30 mhz 0001 12.2?19.5 mhz 0011 7.8?12.5 mhz 0111 5?8 mhz 1111 table 16.3. pll frequency characteristics ?40 to +85 c unless otherwise specified. input frequency (divided reference frequency) pll output frequency *note: the maximum operating frequency of the c8051f366/7/8/9 is 50 mhz. c8051f360/1/2/3/4/5/6/7/8/9 182 rev. 1.0 table 16.4. pll lock timing characteristics ?40 to +85 c unless otherwise specified parameter conditions min typ max units 53 0m h z 25 100* mhz input fre quency multiplier (pll0mul) pll0flt setting output frequency min typ max units 5 mhz 20 0x0f 100 mhz 202 s 13 0x0f 65 mhz 115 s 16 0x1f 80 mhz 241 s 9 0x1f 45 mhz 116 s 12 0x2f 60 mhz 258 s 6 0x2f 30 mhz 112 s 10 0x3f 50 mhz 263 s 5 0x3f 25 mhz 113 s 25 mhz 40 x 0 11 0 0 m h z4 2 s 2 0x01 50 mhz 33 s 3 0x11 75 mhz 48 s 2 0x11 50 mhz 17 s 2 0x21 50 mhz 42 s 1 0x21 25 mhz 33 s 2 0x31 50 mhz 60 s 1 0x31 25 mhz 25 s rev. 1.0 183 c8051f360/1/2/3/4/5/6/7/8/9 17. port input/output digital and analog resources are available throu gh up to 39 i/o pins. on the largest devices (c8051f360/3), port pins are organized as four by te-wide ports and one 7-bit-wide port. on the other devices (c8051f361/2/4 /5/6/7/8/9), port pins are three byte-wide ports and one partial port. each of the port pins can be defined as general-purpose i/o (gpi o) or analog input/output; port pins p0.0?p3.7 can be assigned to one of the internal digital resources as shown in figure 17.3 . the designer has complete control over which functions are assigned, limited only b y the number of physical i/o pins. this resource assignment flexibility is achieved thro ugh the use of a priority crossbar decoder. note that the state of a port i/o pin can always be read in the correspondin g port latch, regardless of the crossbar settings. the crossbar assigns the selected internal digital res our ces to the i/o pins based on the peripheral priority order of the priority decoder ( figure 17.3 and figure 17.4 ). the registers xbr0 and xbr1, defined in sfr definition 17.1 and sfr definition 17.2 , are used to select internal digital functions. all port i/os are 5 v tolerant (refer to figure 17.2 for the port cell circuit). the port i/o cells are configured as either push-pull or open-drain in the port outp u t mode registers (pnmdout, where n = 0,1,2,3,4). com - plete electrical spec ifications for por t i/o are given in ta b l e 17.1 on page 201 . xbr0, xbr1, pnskip registers digital crossbar priority decoder 2 p0 i/o cells p0.0 p0.7 8 p0mask, p0match p1mask, p1match, p2mask, p2match registers uart (internal digital signals) highest priority lowest priority sysclk 2 smbus t0, t1 2 7 pca 4 cp0 cp1 outputs spi 4 (port latches) p0 (p0.0-p0.7) (p1.0-p1.7) 8 8 p1 p2 (p2.0-p2.7) 8 pnmdout, pnmdin registers 3.5?3.7 available on c8051f360/3 p3 (p3.0-p3.7) 8 p1 i/o cells p1.0 p1.7 8 p2 i/o cell 8 p2.0 p2.7 p3 i/o cells p3.0 p3.7 8 3.1?3.4 available on c8051f360/1/3/4/6/8 figure 17.1. port i/o fun ctional block diagram (port 0 through port 3) gnd /port-outenable port-output push-pull vio vio /weak-pullup (weak) port pad analog input analog select port-input c8051f360/1/2/3/4/5/6/7/8/9 184 rev. 1.0 figure 17.2. port i/o cell block diagram rev. 1.0 185 c8051f360/1/2/3/4/5/6/7/8/9 17.1. priority crossbar decoder the priority crossb ar decoder (figure 17.3) assigns a priority to each i/o function , starting at the top with uart0. when a digital resource is selected, the leas t- significant unassigned port pin is assigned to that resource (excluding uart0, which will be assign ed to specific port pins (p0.1 and p0.2 in the c8051f360/3 devices, p0.4 and p0.5 in the c8051f361/2 /4/5/6/7/8/9 devi ces). if a port pin is assigned, the crossbar skips that pin when as signing the next selected resource. additionally, the crossbar will skip port pins whose associated bits in the pnskip regist ers are set. the pnskip registers allow software to skip port pins that are to be used for anal og input, dedicated functions, or gpio. important note on crossbar configuration: i f a port pin is claimed by a peripheral without use of the crossbar, its corresponding pnskip bit should be set. this applies to the port pins associated with the external oscillator, v ref , external cnvstr signal, ida0, and any selected adc or comparator inputs. the crossbar skips selected pins as if they were alre ady assigned, and moves to the next unassigned pin. figure 17.3 shows the crossbar decoder priority with no port pins skipped (p0skip, p1skip, p2skip, p3skip = 0x00); figure 17.4 shows the crossbar decoder priority with the p1.0 and p1.1 pins skipped (p1skip = 0x03). vref ida0 xtal1 xtal2 cnvstr ale vref ida0 xtal1 xtal2 cnvstr 01234567012345670123456701234567 (*4-wire spi only) cp0 cp0a cp1 cp1a /sysclk cex0 cex1 cex2 cex3 cex4 cex5 eci t0 t1 00000000000000000000000000000000 p3 p3skip[0:7] p3.1-p3.4 available on 32/48-pin only p3.5-p3.7 available on 48-pin only p2 p2skip[0:7] (48-pin package) (32-pin and 28-pin packages) p0 p1 p1skip[0:7] nss* sck miso mosi rx0 sf signals (32- and 28- pin) pin i/o tx0 sf signals (48-pin) tx0 rx0 sda p0skip[0:7] scl figure 17.3. crossbar priority decoder with no pins skipped vref ida0 xtal1 xtal2 cnvstr ale vref ida0 xtal1 xtal2 cnvstr 01234567012345670123456701234567 (*4-wire spi only) cp0 cp0a cp1 cp1a /sysclk cex0 cex1 cex2 cex3 cex4 cex5 eci t0 t1 00000000110000000000000000000000 p3 p3skip[0:7] p3.1-p3.4 available on 32/48-pin only p3.5-p3.7 available on 48-pin only p2 p2skip[0:7] (48-pin package) (32-pin and 28-pin packages) p0 p1 p1skip[0:7] nss* sck miso mosi rx0 sf signals (32- and 28- pin) pin i/o tx0 sf signals (48-pin) tx0 rx0 sda p0skip[0:7] scl c8051f360/1/2/3/4/5/6/7/8/9 186 rev. 1.0 figure 17.4. crossbar priority decoder with port pins skipped registers xbr0 and xbr1 are used to assign the digital i/o resources to the physical i/o port pins. note that when the smbus is selected, the crossbar assi gns both pins associated with the smbus (sda and scl); when the uart is selected, the crossbar assign s both pins associated with the uart (tx and rx). uart0 pin assignments are fixed for bootloading purposes: uart tx0 is always assigned to p0.1 (c8051f360/3) or p0.4 (c8051f361/2/4/5/6/7/8/9); uart rx0 is always assigned to p0.2 (c8051f360/3) or p0.5 (c8051f361/2/4/5/6/7/8/9). st andard port i/os appear co ntiguously starting at p0.0 after prioritized functions and skipped pins are assigned. important note: th e spi can be operated in either 3-wire or 4-wire modes, depending on the state of the nssmd1-nssmd0 bits in register spi 0cn. according to the spi mode, the nss signal may or may not be routed to a port pin. rev. 1.0 187 c8051f360/1/2/3/4/5/6/7/8/9 17.2. port i/o initialization port i/o initialization cons ists of the following steps: step 1. select the input mode (analog or digital) for all port pins, using the port input mode re gister (pnmdin). step 2. select the output mode (open-drain or push -pull) for all port pins, using the port output mode register (pnmdout). step 3. select any pins to be skipped by the i/o crossbar using the port skip registers (pnskip). step 4. assign port pins to desir ed peripherals using the xbrn registers. step 5. enable the cr ossbar (xbare = ?1?). all port pins must be configured as either analog or dig ital inputs. any pins to be used as comparator or adc inputs should be configured as an analog inputs. when a pin is configured as an analog input, its weak pullup, digital driver, and digital receiver are disabled. this process save s power and reduces noise on the analog input. pins configured as digital inputs may still be used by analog peripherals; however, this practice is not recommended. additionally, all analog input pins should be configur ed to be skipped by the crossbar (accomplished by setting the associated bits in pnskip). port input mode is set in the pnmdin register, where a ?1? indicates a digital input, and a ?0? indicates an analog input. all pins default to digital inputs on reset. see sfr defini - tion 17.4 for the pnmdin register details. the output driver characteristics of the i/o pins ar e d efined using the port output mode registers (pnmd - out). each port output driver can be configured as either open drain or push- pull. this selection is required even for the digital resources selected in the xbrn registers, and is not automatic. the only exception to this is the smbus (sda, scl) pins, which are configured as open-drain regardless of the pnmdout settings. when the weakpud bi t in xbr1 is ?0?, a weak pullup is enabled for all port i/o con - figured as open-drain. w eakpud does not affect the push-pull port i/o. furthermo re, the weak pullup is turned off on an output that is driving a ?0? and for pins configured for analog input mode to avoid unneces - sary power dissipation. registers xbr0 and xbr1 must be loaded with the approp r iate values to select the digital i/o functions required by the design. setting the xbare bit in xbr1 to ?1? enables the cross bar. until the crossbar is enabled, the external pins remain as standard port i/o (in input mode), regardless of the xbrn register settings. for given xbrn register settings, one can de termine the i/o pin-out us ing the priority decode table; as an alternative, the confi guration wizard utility of the silicon labs ide software will determine the port i/o pin-assignments based on the xbrn register settings. the crossbar must be enabled to use port pins as standard port i/o in output mode. port output drivers are disabled while the crossbar is disabled. c8051f360/1/2/3/4/5/6/7/8/9 188 rev. 1.0 sfr definition 17.1. xbr0: port i/o cro ssb ar register 0 bit 7: cp1ae: comparator1 asynchronous output enable 0: asynchronous cp1 unavailable at port pin. 1: asynchronous cp1 routed to port pin. bit 6: cp1e: comparator1 output enable 0: cp1 unavailable at port pin. 1: cp1 routed to port pin. bit 5: cp0ae: comparator0 asynchronous output enable 0: asynchronous cp0 unavailable at port pin. 1: asynchronous cp0 routed to port pin. bit 4: cp0e: comparator0 output enable 0: cp0 unavailable at port pin. 1: cp0 routed to port pin. bit 3: syscke: /sysclk output enable 0: /sysclk unavaila ble at port pin. 1: /sysclk (divided by 1, 2, 4, or 8) routed to port pin. the divide factor is determined by the clkdiv1?0 bits in regi ster clksel (see section se ction ?16. oscillators? on page 169). bit 2: smb0e: smbus i/o enable 0: smbus i/o unavailable at port pins. 1: smbus i/o routed to port pins. bit 1: spi0e: spi i/o enable 0: spi i/o unavailable at port pins. 1: spi i/o routed to port pins. note that t he spi can be assigned either 3 or 4 gpio pins. bit 0: urt0e: uart i/o output enable 0: uart i/o unavailable at port pin. 1: uart tx0, rx0 routed to port pins p0.1 and p0.2 (c8051f360/3) or p0.4 and p0.5 (c8051f361/2/4/5/6/7/8/9). sfr page: sfr address: f 0xe1 r/w r/w r/w r/w r/w r/w r/w r/w reset value cp1ae cp1e cp0ae cp0e syscke smb0e spi0e urt0e 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rev. 1.0 189 c8051f360/1/2/3/4/5/6/7/8/9 sfr definition 17.2. xbr1: port i/o cro ssb ar register 1 bit 7: weakpud: port i/ o weak pullup disable. 0: weak pullups enabled (except for ports whose i/o are configured as analog input). 1: weak pullups disabled. bit 6: xbare: cros sbar enable. 0: crossbar disabled. 1: crossbar enabled. bit 5: t1e: t1 enable 0: t1 unavailable at port pin. 1: t1 routed to port pin. bit 4: t0e: t0 enable 0: t0 unavailable at port pin. 1: t0 routed to port pin. bit 3: ecie: pca0 external counter input enable 0: eci unavailable at port pin. 1: eci routed to port pin. bits 2?0: pca0me: pca module i/o enable bits. 000: all pca i/o unavailable at port pins. 001: cex0 routed to port pin. 010: cex0, cex1 ro uted to port pins. 011: cex0, cex1, cex2 routed to port pins. 100: cex0, cex1, cex2, cex3 routed to port pins. 101: cex0, cex1, cex2, cex3, cex4 routed to port pins. 110: cex0, cex1, cex2, cex3, cex4 , cex5 routed to port pins. 111: reserved. sfr page: sfr address: f 0xe2 r/w r/w r/w r/w r/w r/w r/w r/w reset value weakpud xbare t1e t0e ecie pca0me 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 c8051f360/1/2/3/4/5/6/7/8/9 190 rev. 1.0 17.3. general purpose port i/o port pins that remain unassigned by the crossbar and are not used by analog peripherals can be used for general purpose i/o. ports p0-p3 are accessed through corresponding special function registers (sfrs) that are both byte-addressable and bit-addressable. port 4 (c8051f360/3 only) uses an sfr which is byte-addressable. when writing to a port, the value wr itten to the sfr is latched to maintain the output data value at each pin. when reading, the logic levels of the port's input pins are returned regardless of the xbrn settings (i.e., even when the pin is assigned to another signal by the crossbar, the port register can always read its corresponding port i/o pin). the except ion to this is the executio n of the read-modify-write instructions that target a port latc h register as the destination. the read-modify-write in structions when operating on a port sfr are the following: anl, orl, xrl, jbc, cpl, inc, dec, djnz and mov, clr or setb, when the destination is an individual bit in a po rt sfr. for these instructions, the value of the latch register (not the pin) is read, modified, and written back to the sfr. in addition to performing general purpose i/o, p0, p1 , a nd p2 can generate a port match event if the logic levels of the port?s input pins match a software controlled value. a port match event is generated if (p0 & p0mask) does not equal (p0match & p0mask), if (p1 & p1mask) does not equal (p1 match & p1mask), or if (p2 & p2mask) does not equal (p2match & p2mask). this allows soft - ware to be notified if a certain change or pattern occurs on p0, p1, or p2 input pins regardless of the xbrn se ttings. a port match event can cause an interrupt if emat (eie2.1) is set to '1' or cause the internal oscil - lator to awaken from suspend mode. see section ?16.1.1. internal oscillator suspend mode? on page 170 for more information. sfr definition 17.3. p0: port0 bits 7?0: p0.[7:0] write - output appears on i/o pins per crossbar registers. 0: logic low output. 1: logic high output (high impedance if corresponding p0mdout.n bit = 0). read - always reads ?0? if selected as analog input in register p0mdin. directly reads port pin when configured as digital input. 0: p0.n pin is logic low. 1: p0.n pin is logic high. sfr page: sfr address: all pages 0x80 (bit addressable) r/w r/w r/w r/w r/w r/w r/w r/w reset value p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rev. 1.0 191 c8051f360/1/2/3/4/5/6/7/8/9 sfr definition 17.4. p0mdin: port0 input mode bits 7?0: analog input configurati on bits for p0.7-p0.0 (respectively). port pins configured as analog inputs have their weak pullup, digital driver, and digital receiver disabled. 0: corresponding p0.n pin is co nfigured as an analog input. 1: corresponding p0.n pin is not configured as an analog input. sfr page: sfr address: f 0xf1 r/w r/w r/w r/w r/w r/w r/w r/w reset value 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr definition 17.5. p0mdout: port0 output mode bits 7?0: output configuration bits for p0.7-p0.0 (r espectively): ignored if corresponding bit in regis- ter p0mdin is logic ?0?. 0: corresponding p0.n output is open-drain. 1: corresponding p0.n output is push-pull. note: when sda and scl appear on any of the port i/o, each are open-drain regardless of the value of p0mdout. sfr page: sfr address: f 0xa4 r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 c8051f360/1/2/3/4/5/6/7/8/9 192 rev. 1.0 sfr definition 17.6. p0skip: port0 skip bits 7?0: p0skip[7:0]: port0 crossbar skip enable bits. these bits select port pins to be skipped by the crossbar decoder. port pins used as ana- log inputs (for adc or comparator) or used as special functions (v ref input, external oscil- lator circuit, cnvstr input) should be skipped by the crossbar. 0: corresponding p0.n pin is not skipped by the crossbar. 1: corresponding p0.n pin is skipped by the crossbar. sfr page: sfr address: f 0xd4 r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr definition 17.7. p0mat: port0 match bits 7?0: p0mat[7:0]: port0 match value. these bits control the value that unmasked p0 port pins are compared against. a port match event is generated if (p0 & p0mask) does not equal (p0mat & p0mask). sfr page: sfr address: 0 0xf3 r/w r/w r/w r/w r/w r/w r/w r/w reset value 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr definition 17.8. p0mask: port0 mask bits 7?0: p0mask[7:0]: port0 mask value. these bits select which port pins will be compared to the value stored in p0mat. 0: corresponding p0.n pin is ignore d and cannot cause a port match event. 1: corresponding p0.n pin is compared to the corresponding bit in p0mat. sfr page: sfr address: 0 0xf4 r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rev. 1.0 193 c8051f360/1/2/3/4/5/6/7/8/9 sfr definition 17.9. p1: port1 bits 7?0: p1.[7:0] write - output appears on i/o pins per crossbar registers. 0: logic low output. 1: logic high output (high impedance if corresponding p1mdout.n bit = 0). read - always reads ?0? if selected as analog input in register p1mdin. directly reads port pin when configured as digital input. 0: p1.n pin is logic low. 1: p1.n pin is logic high. sfr page: sfr address: all pages 0x90 (bit addressable) r/w r/w r/w r/w r/w r/w r/w r/w reset value p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr definition 17.10. p1mdin: port1 input mode bits 7?0: analog input configurati on bits for p1.7-p1.0 (respectively). port pins configured as analog inputs have their weak pullup, digital driver, and digital receiver disabled. 0: corresponding p1.n pin is co nfigured as an analog input. 1: corresponding p1.n pin is not configured as an analog input. sfr page: sfr address: f 0xf2 r/w r/w r/w r/w r/w r/w r/w r/w reset value 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 c8051f360/1/2/3/4/5/6/7/8/9 194 rev. 1.0 sfr definition 17.11. p1mdout: port1 output mode bits 7?0: output configuration bits for p1.7-p1.0 (r espectively): ignored if corresponding bit in regis- ter p1mdin is logic ?0?. 0: corresponding p1.n output is open-drain. 1: corresponding p1.n output is push-pull. sfr page: sfr address: f 0xa5 r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr definition 17.12. p1skip: port1 skip bits 7?0: p1skip[7:0]: port1 crossbar skip enable bits. these bits select port pins to be skipped by the crossbar decoder. port pins used as ana- log inputs (for adc or comparator) or used as special functions (v ref input, external oscil- lator circuit, cnvstr input) should be skipped by the crossbar. 0: corresponding p1.n pin is not skipped by the crossbar. 1: corresponding p1.n pin is skipped by the crossbar. sfr page: sfr address: f 0xd5 r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr definition 17.13. p1mat: port1 match bits 7?0: p1mat[7:0]: port1 match value. these bits control the value that unmasked p0 port pins are compared against. a port match event is generated if (p1 & p1mask) does not equal (p1mat & p1mask). sfr page: sfr address: 0 0xe1 r/w r/w r/w r/w r/w r/w r/w r/w reset value 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rev. 1.0 195 c8051f360/1/2/3/4/5/6/7/8/9 sfr definition 17.14. p1mask: port1 mask bits 7?0: p1mask[7:0]: port1 mask value. these bits select which port pins will be compared to the value stored in p1mat. 0: corresponding p1.n pin is ignore d and cannot cause a port match event. 1: corresponding p1.n pin is compared to the corresponding bit in p1mat. sfr page: sfr address: 0 0xe2 r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr definition 17.15. p2: port2 bits 7?0: p2.[7:0] write - output appears on i/o pins per crossbar registers. 0: logic low output. 1: logic high output (high impedance if corresponding p2mdout.n bit = 0). read - always reads ?0? if selected as analog input in register p2mdin. directly reads port pin when configured as digital input. 0: p2.n pin is logic low. 1: p2.n pin is logic high. sfr page: sfr address: all pages 0xa0 (bit addressable) r/w r/w r/w r/w r/w r/w r/w r/w reset value p2.7 p2.6 p2.5 p2.4 p2.3 p2.2 p2.1 p2.0 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 c8051f360/1/2/3/4/5/6/7/8/9 196 rev. 1.0 sfr definition 17.16. p2mdin: port2 input mode bits 7?0: analog input configurati on bits for p2.7-p2.0 (respectively). port pins configured as analog inputs have their weak pullup, digital driver, and digital receiver disabled. 0: corresponding p2.n pin is co nfigured as an analog input. 1: corresponding p2.n pin is not configured as an analog input. sfr page: sfr address: f 0xf3 r/w r/w r/w r/w r/w r/w r/w r/w reset value 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr definition 17.17. p2mdout: port2 output mode bits 7?0: output configuration bits for p2.7-p2.0 (r espectively): ignored if corresponding bit in regis- ter p2mdin is logic ?0?. 0: corresponding p2.n output is open-drain. 1: corresponding p2.n output is push-pull. sfr page: sfr address: f 0xa6 r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rev. 1.0 197 c8051f360/1/2/3/4/5/6/7/8/9 sfr definition 17.18. p2skip: port2 skip bits 7?0: p2skip[7:0]: port2 crossbar skip enable bits. these bits select port pins to be skipped by the crossbar decoder. port pins used as ana- log inputs (for adc or comparator) or used as special functions (v ref input, external oscil- lator circuit, cnvstr input) should be skipped by the crossbar. 0: corresponding p2.n pin is not skipped by the crossbar. 1: corresponding p2.n pin is skipped by the crossbar. sfr page: sfr address: f 0xd6 r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr definition 17.19. p2mat: port2 match bits 7?0: p2mat[7:0]: port2 match value. these bits control the value that unmasked p2 port pins are compared against. a port match event is generated if (p2 & p2mask) does not equal (p2mat & p2mask). sfr page: sfr address: 0 0xb1 r/w r/w r/w r/w r/w r/w r/w r/w reset value 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr definition 17.20. bits 7?0: p2mask[7:0]: port2 mask value. these bits select which port pins will be compared to the value stored in p2mat. 0: corresponding p2.n pin is ignore d and cannot cause a port match event. 1: corresponding p2.n pin is compared to the corresponding bit in p2mat. sfr page: sfr address: 0 0xb2 r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 p2mask: port2 mask c8051f360/1/2/3/4/5/6/7/8/9 198 rev. 1.0 sfr definition 17.21. bits 7?0: p3.[7:0] write - output appears on i/o pins per crossbar registers. 0: logic low output. 1: logic high output (high impedance if corresponding p3mdout.n bit = 0). read - always reads ?0? if selected as analog input in register p3mdin. directly reads port pin when configured as digital input. 0: p3.n pin is logic low. 1: p3.n pin is logic high. sfr page: sfr address: all pages 0xb0 (bit addressable) r/w r/w r/w r/w r/w r/w r/w r/w reset value p3.7 p3.6 p3.5 p3.4 p3.3 p3.2 p3.1 p3.0 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 p3: port3 sfr definition 17.22. bits 7?0: analog input configurati on bits for p3.7-p3.0 (respectively). port pins configured as analog inputs have their weak pullup, digital driver, and digital receiver disabled. 0: corresponding p3.n pin is co nfigured as an analog input. 1: corresponding p3.n pin is not configured as an analog input. sfr page: sfr address: f 0xf4 r/w r/w r/w r/w r/w r/w r/w r/w reset value 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 p3mdin: port3 input mode rev. 1.0 199 c8051f360/1/2/3/4/5/6/7/8/9 sfr definition 17.23. bits 7?0: output configuration bits for p3.7-p3.0 (r espectively): ignored if corresponding bit in regis- ter p3mdin is logic ?0?. 0: corresponding p3.n output is open-drain. 1: corresponding p3.n output is push-pull. sfr page: sfr address: f 0xaf r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 p3mdout: port3 output mode sfr definition 17.24. p3skip: port3 skip bits 7?0: p3skip[7:0]: port3 crossbar skip enable bits. these bits select port pins to be skipped by the crossbar decoder. port pins used as ana- log inputs (for adc or comparator ) or used as special functions (v ref input, external oscil- lator circuit, cnvstr input) should be skipped by the crossbar. 0: corresponding p3.n pin is not skipped by the crossbar. 1: corresponding p3.n pin is skipped by the crossbar. sfr page: sfr address: f 0xd7 r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 c8051f360/1/2/3/4/5/6/7/8/9 200 rev. 1.0 sfr definition 17.25. bit 7: unused. read = 0b. write = don?t care. bits 6?0: p4.[6:0] write - output appears on i/o pins per crossbar registers. 0: logic low output. 1: logic high output (high impedance if corresponding p4mdout.n bit = 0). read - directly reads port pin. 0: p4.n pin is logic low. 1: p4.n pin is logic high. sfr page: sfr address: all pages 0xb5 r r/w r/w r/w r/w r/w r/w r/w reset value ? p4.6 p4.5 p4.4 p4.3 p4.2 p4.1 p4.0 01111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 p4: port4 sfr definition 17.26. bit 7: unused. read = 0b. write = don?t care. bits 6?0: output configuration bi ts for p4.6-p4.0 (respectively). 0: corresponding p4.n output is open-drain. 1: corresponding p4.n output is push-pull. sfr page: sfr address: f 0xae r r/w r/w r/w r/w r/w r/w r/w reset value ? 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 p4mdout: port4 output mode table 17.1. port i/o dc electri cal characteristics v dd = 2.7 to 3.6 v, ?40 to +85 c unless otherwise specified. rev. 1.0 201 c8051f360/1/2/3/4/5/6/7/8/9 parameters conditions min typ max units output high voltage i oh = ?3 ma, port i/o push-pull i oh = ?10 a, port i/o push-pull i oh = ?10 ma, port i/o push-pull v dd ? 0.7 v dd ? 0.1 ? ? ? v dd ? 0.8 ? ? ? v output low voltage i ol = 8.5 ma i ol = 10 a i ol = 25 ma ? ? ? ? ? 1.0 0.6 0.1 ? v input high voltage 2.0 ? ? v input low voltage ? ? 0.8 v input leakage current weak pullup off weak pullup on, v in = 0 v ? ? ? 25 1 50 a c8051f360/1/2/3/4/5/6/7/8/9 202 rev. 1.0 18. smbus the smbus i/o interface is a two-wire, bi-directional serial bus. the smbus is compliant with the system management bus specification, version 1.1, and compatible with the i 2 c serial bus. reads and writes to the interface by the system contro ller are byte oriented with the smbu s interface autonom ously controlling the serial transfer of the data. data can be transferre d at up to 1/10th of the system clock as a master or slave (this can be faster than allowed by the smbus specification, depending on the system clock used). a method of extending the clock-low duration is ava ilable to accommodate devices with different speed capabilities on the same bus. the smbus interface may operate as a master and/or sla ve, and may function on a bus with multiple mas - ters. the smbus provides control of sda (serial data), scl ( serial clock) generation and synchronization, arbitration logic, and start/stop control and gene ration. three sfrs are associated with the smbus: smb0cf configures the sm bus; smb0cn controls the status of the smbus; and smb0dat is the data register, used for both transmitting and receiving smbus data and slave addresses. data path control smbus control logic c r o s s b a r scl filter n sda control scl control arbitration scl synchronization irq generation scl generation (master mode) sda control interrupt request port i/o smb0cn s t a a c k r q a r b l o s t a c k s i t x m o d e m a s t e r s t o 01 00 10 11 t0 overflow t1 overflow tmr2h overflow tmr2l overflow smb0cf e n s m b i n h b u s y e x t h o l d s m b t o e s m b f t e s m b c s 1 s m b c s 0 0 1 2 3 4 5 6 7 smb0dat sda filter n figure 18.1. smbus block diagram rev. 1.0 203 c8051f360/1/2/3/4/5/6/7/8/9 18.1. supporting documents it is assumed the reader is fam iliar with or has access to th e following supporting documents: 1. the i 2 c-bus and how to use it (including specifications), ph ilips semiconductor. 2. the i 2 c-bus specification?version 2.0, philips semiconductor. 3. system management bus specification?v ersion 1.1, sbs implementers forum. 18.2. smbus configuration figure 18.2 shows a typical smbus configuration. the sm bus s pecification allows any recessive voltage between 3.0 v and 5.0 v; different devices on the bus may operate at different voltage levels. the bi-direc - tional scl (serial clock) and sda (serial data) lines mu st b e connected to a positive power supply voltage through a pullup resistor or similar circuit. every devi ce connected to the bus must have an open-drain or open-collector output for both the scl and sda lines, so that both are pulled high (recessive state) when the bus is free. the maximum number of devices on the bus is limited only by the requirement that the rise and fall times on the bus not exceed 300 ns and 1000 ns, respectively. v dd = 5 v master device slave device 1 slave device 2 v dd = 3 v v dd = 5 v v dd = 3 v sda scl figure 18.2. typical smbus configuration 18.3. smbus operation two types of data transfers are possible: data transfers from a master transmitter to an addressed slave receiver (write), and data transfers from an addres sed slave transmitter to a master receiver (read). the master device initiates both types of data transfer s and provides the serial clock pulses on scl. the smbus interface may operate as a master or a slave, and multiple master devices on the same bus are supported. if two or more masters attempt to initiate a data transfer simultaneously, an arbitration scheme is employed with a single master always winning the arbitr ation. note that it is not necessary to specify one device as the master in a system ; any device who transmits a star t and a slave address becomes the master for the duration of that transfer. a typical smbus transaction consists of a start cond itio n followed by an address byte (bits7?1: 7-bit slave address; bit0: r/w direction bit), one or more byte s of data, and a stop condition. each byte that is received (by a master or slave) must be acknow ledged (ack) with a low sda during a high scl (see figure 18.3 ). if the receiving device does not ack, the transmitting device will read a nack (not acknowl - edge), which is a high sda during a high scl. c8051f360/1/2/3/4/5/6/7/8/9 204 rev. 1.0 the direction bit (r/w) occupies the least-significant bit position of the address byte. the direction bit is set to logic ?1? to indicate a "read" operation and cleared to logic ?0? to indicate a "write" operation. all transactions are initiated by a master, with one or more addressed slave devices as the target. the master generates the start condition and then transmits the slave address and direction bit. if the trans - action is a write operation from the ma ster to the slave, the master tr ansmits the data a byte at a time waiting for an ack from the slave at the end of each byte. for read operations , the slave transmits the data waiting for an ack from the master at the end of each byte. at the end of the data transfer, the master generates a stop condition to terminate the transaction and free the bus. figure 18.3 illustrates a typical smbus transaction. sla6 sda sla5-0 r/w d7 d6-0 scl slave address + r/w data byte start ack nack stop figure 18.3. smbus transaction 18.3.1. arbitration a master may start a transfer only if the bus is free. th e bus is free after a stop condition or after the scl and sda lines remain high for a specified time (see section ?18.3.4. scl high (smbus free) timeout? on page 205 ). in the event that two or more devices attempt to begin a transfer at the same time, an arbitra - tion scheme is employed to force one master to give u p the bus. the master devices continue transmitting until one attempts a high while the other transmits a low. since the bus is open-drain, the bus will be pulled low. the master attempting th e high will detect a low sda and lo se the arbitration. the winning master continues its transmission without interruption; the losing master becomes a slave and receives the rest of the transfer if addressed. this arbitration scheme is non-destru ctive: one device always wins, and no data is lost. 18.3.2. clock low extension smbus provides a clock synchronizati on mechanism, similar to i2c, wh ich allows devices with different speed capabilities to coexist on the bus. a clock-low extension is used du ring a transfer in order to allow slower slave devices to communica te with faster masters. the slave may temporarily hold the scl line low to extend the clock low period, effectively decreasing the serial clock frequency. 18.3.3. scl low timeout if the scl line is held low by a slave device on the bus, no further communication is possible. furthermore, the master cannot force the scl line high to correct th e error condition. to solve this problem, the smbus protocol specifies that devices participating in a tran sfer must detect any clock cy cle held low longer than 25 ms as a ?timeout? condition. devices that have det ected the timeout condition must reset the communi - cation no later than 10 ms after detecting the timeout condition. when the smbtoe bit in smb0cf is set, timer 3 is used to detect scl low timeouts. timer 3 is forced to r eload when scl is high, and allowed to count when scl is low. with timer 3 enabled and configured to rev. 1.0 205 c8051f360/1/2/3/4/5/6/7/8/9 overflow after 25 ms (and smbtoe set), the timer 3 interrupt service routine can be used to reset (disable a nd re-enable) the smbus in the event of an scl low timeout. 18.3.4. scl high (smbus free) timeout the smbus specification stipulates that if the scl and sda lines remain high for more that 50 s, the bus is des ignated as free. when the sm bfte bit in smb0cf is set, the bu s will be considered free if scl and sda remain high for more than 10 smbus clock source periods. if the smbus is waiting to generate a master st art, the start will be generated following this timeout. note that a clock source is required for free timeout detection, even in a slave-only implementation. 18.4. using the smbus the smbus can operate in both master and slave modes. the interface provides timing and shifting con - trol for serial transfers; higher level protocol is dete rm ined by user software. the smbus interface provides the following application-independent features: ? byte-wise serial data transfers ? clock signal generation on scl (master mode only) and sda data synchronization ? timeout/bus error recognition, as define d by the smb0cf configuration register ? start/stop timing, detection, and generation ? bus arbitration ? interrupt generation ? status information smbus interrupts are generated for each data byte or slave ad dress that is transf erred. when transmitting, this interrupt is generated after the ack cycle so th at software may read the received ack value; when receiving data, this interrupt is generated before t he ack cycle so that software may define the outgoing ack value. see section ?18.5. smbus transfer modes? on page 213 for more details on transmission sequences. interrupts are also generated to indicate the beginning of a transfer when a master (start generated), or the end of a transfer when a slave (stop detected) . software should read the smb0cn (smbus control register) to find the cause of the smbus inte rrupt. the smb0cn register is described in section ?18.4.2. smb0cn control register? on page 209 ; ta b l e 18.4 provides a quick smb0cn decoding refer - ence. smbus configuration options include: ? timeout detection (scl low timeout and/or bus free timeout) ? sda setup and hold time extensions ? slave event enable/disable ? clock source selection these options are selected in the smb0cf re giste r, as described in section ?18.4.1. smbus configuration register? on page 206 . c8051f360/1/2/3/4/5/6/7/8/9 206 rev. 1.0 18.4.1. smbus configuration register the smbus configuration register (s mb0cf) is used to enable the smbus master and/or slave modes, select the smbus clock source, and select the smbus timing and timeout options . when the ensmb bit is set, the smbus is enabled for all master and slave events. slave events may be disabled by setting the inh bit. with slave events inhibited, the smbus in terface will still monitor the scl and sda pins; however, the interface will nack all received addresses and will not generate any slave inte rrupts. when the inh bit is set, all slave events will be inhibited following the ne xt start (interrupts will cont inue for the duration of the current transfer). table 18.1. smbus clock source selection the smbcs1?0 bits select the smbus clock source, which is used only when operating as a master or when the free timeout detection is enabled. when op erating as a master, overflows from the selected source determine the absolute minimum scl low and high times as defined in equation 18.1 . note that the selected clock source may be shared by other peripherals so long as the timer is left running at all times. for example, timer 1 overflows may generate the smbus and uar t baud rates simultaneously. timer configuration is covered in section ?21. timers? on page 247 . t highmin t lowmin 1 f clocksourceoverflow ---------------------------------- ----------- - == equation 18.1. minimum scl high and low t imes the selected clock source should be configured to establish the minimum scl high and low times as per equation 18.1 . when the interface is operating as a master ( and scl is not driven or extended by any other devices on the bus), the typica l smbus bit rate is app roximated by equation 18.2 . bitrate f clocksourceoverflow 3 --------------- ------------------------------ - = equation 18.2. typical smbus bit rate smbcs1 smbcs0 smbus clock source 0 0 timer 0 overflow 0 1 timer 1 overflow 1 0 timer 2 high byte overflow 1 1 timer 2 low byte overflow rev. 1.0 207 c8051f360/1/2/3/4/5/6/7/8/9 figure 18.4 shows the typical scl generation described by equation 18.2. notice that t high is typically twice as large as t low . the actual scl output may vary due to other devices on the bus (scl may be extended low by slower slave devices, or driven low by contending master devices). the bit rate when operating as a master will never exce ed the limits defined by equation equation 18.1 . scl timer source overflows scl high timeout t low t high figure 18.4. typical smbus scl generation setting the exthold bit extends the minimum setup and hold times for the sda line. the minimum sda setup time defines the absolute mini mum time that sda is stable before scl transitions from low-to-high. the minimum sda hold time defines the absolute minimum time that the current sda value remains stable after scl transitions from high-to-low. exthold should be set so that the minimum setup and hold times meet the smbus specification requirements of 250 ns and 300 ns, respectively. ta b l e 18.2 shows the min - imum setup and hold times for the two exthold settings. setup and hold time extensions are typically necessary when sysclk is above 10 mhz. table 18.2. minimum sda setup and hold times *note: setup time for ack bit transmissions and the msb of all data transfers. the s/w delay occurs between the time smb0dat or ack is written and when si is cleared. note that if si is cleared in the same wr ite that defines the ou tgoing ack value, s/w delay is zero. with the smbtoe bit set, timer 3 should be configured to overflow after 25 ms in order to detect scl low time outs (see section ?18.3.3. scl low timeout? on page 204 ). the smbus interface will force timer 3 to reload while scl is high, and allow timer 3 to count when scl is low. the timer 3 interrupt service routine sho uld be used to reset smbus communication by disabling and re-enabling the smbus. smbus free timeout detection can be enabled by setting the smbfte bit. when this bit is s et, the bus will be considered free if sda and scl remain high for more than 10 smbus clock source periods (see figure 18.4 ). when a free timeout is dete cted, the interface will res pond as if a stop was detected (an interrupt will be generat ed, and st o will be set). exthold minimum sda setup time minimum sda hold time 0 t low ? 4 system clocks or 1 system clock + s/w delay* 3 system clocks 1 11 system clocks 12 system clocks c8051f360/1/2/3/4/5/6/7/8/9 208 rev. 1.0 sfr definition 18.1. smb0cf: smbus clock/configuration bit 7: ensmb: smbus enable. this bit enables/disables the smbus interface. when enabled, the interface constantly mon- itors the sda and scl pins. 0: smbus interface disabled. 1: smbus interface enabled. bit 6: inh: smbus slave inhibit. when this bit is set to logic ?1?, the smbus does not generate an interrupt when slave events occur. this effectively removes the smbus slave from the bus. master mode interrupts are not affected. 0: smbus slave mode enabled. 1: smbus slave mode inhibited. bit 5: busy: smbus busy indicator. this bit is set to logic ?1? by ha rdware when a transfer is in prog ress. it is cleared to logic ?0? when a stop or free-timeout is sensed. bit 4: exthold: smbus setup and hold time extension enable. this bit controls the sda setup and hold times according to: 0: sda extended setup and hold times disabled. 1: sda extended setup and hold times enabled. bit 3: smbtoe: smbus scl ti meout detection enable. this bit enables scl low timeout detection. if set to logic ?1?, the smbus forces timer 3 to reload while scl is high and allows timer 3 to count when scl goes low. if timer 3 is con- figured to split mode, only the high byte of th e timer is held in reload while scl is high. timer 3 should be programmed to generate interrupts at 25 ms, and the timer 3 interrupt service routine should reset smbus communication. bit 2: smbfte: smbus free timeout detection enable. when this bit is set to logic ?1?, the bus will be considered fr ee if scl and sda remain high for more than 10 smbu s clock source periods. bits 1?0: smbcs1?smbcs0: smbu s clock source selection. these two bits select the smbus clock source , which is used to generate the smbus bit rate. the selected device should be configured according to equation 18.1. sfr page: sfr address: all pages 0xc1 r/w r/w r r/w r/w r/w r/w r/w reset value ensmb inh busy exthold smbtoe sm bfte smbcs1 smbcs0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 smbcs1 smbcs0 smbus clock source 0 0 timer 0 overflow 0 1 timer 1 overflow 1 0 timer 2 high byte overflow 1 1 timer 2 low byte overflow rev. 1.0 209 c8051f360/1/2/3/4/5/6/7/8/9 18.4.2. smb0cn control register smb0cn is used to control the interface and to provid e status information (see sfr definition 18.2). the higher four bits of smb0cn (master, txmode, sta, and sto) form a status vector that can be used to jump to servic e routines. master and txmode indi cate the master/slave state and transmit/receive modes, respectively. sta and sto indicate that a start and/or stop ha s been detected or generated since the last smbus interrupt. sta and sto are also used to generate start and stop conditions when operating as a mas - ter. writing a ?1? to sta will cause the smbus interfac e to enter mas ter mode and generate a start when the bus becomes free (sta is not cleared by hardware after the start is generated). writing a ?1? to sto while in master mode will cause the interface to generate a stop and end the current transfer after the next ack cycle. if sto and sta are both set (while in master mode), a stop followed by a start will be generated. as a receiver, writing the ack bit defines the outgoing ack value; as a transmitter, reading the ack bit indicates the value received on the last ack cycle. ackrq is set each time a byte is received, indicating that an outgoing ack value is needed. when ackrq is set, software should write the desired outgoing value to the ack bit before clearing si. a nack will be generated if so ftware does not write the ack bit before clearing si. sda will reflec t the defined ack value immediately following a write to the ack bit; however scl will remain low un til si is cleared. if a received slave address is not acknowledged, further slave events will be ignored unt il the next start is detected. the arblost bit indicates that the interface has lost an arbitration. this may occur anytime the interface is transmitting (master or slave). a lost arbitratio n while operating as a slave indicates a bus error condi - tion. arblost is cleared by hardware each time si is cleared. the si bit (smbus interrupt flag) is set at the beginning and end of each transfer, after each byte frame, or when an arbitration is lost; see ta b l e 18.3 for more details. important note about the si bit: the smbus interface is stalled while si is set; thus scl is held low, and the bus is stalled until software clears si. ta b l e 18.3 lists all sources for hardware changes to the smb0cn bits. refer to table 18.4 for smbus sta - tus decoding using the smb0cn register. c8051f360/1/2/3/4/5/6/7/8/9 210 rev. 1.0 sfr definition 18.2. smb0cn: smbus control bit 7: master: smbus master/slave indicator. this read-only bit indicates when the smbus is operating as a master. 0: smbus operating in slave mode. 1: smbus operating in master mode. bit 6: txmode: smbus transmit mode indicator. this read-only bit indicates when the smbus is operating as a transmitter. 0: smbus in receiver mode. 1: smbus in transmitter mode. bit 5: sta: smbus start flag. write: 0: no start generated. 1: when operating as a master, a start condition is transmitted if the bus is free (if the bus is not free, the start is transmitted after a st op is received or a timeout is detected). if sta is set by software as an active master, a repeated start will be generated after the next ack cycle. read: 0: no start or repeated start detected. 1: start or repeated start detected. bit 4: sto: smbus stop flag. write: 0: no stop condition is transmitted. 1: setting sto to logic ?1? causes a stop condi tion to be transmitted after the next ack cycle. when the stop condition is generated, hardware clears sto to logic ?0?. if both sta and sto are set, a stop condition is transmitted followed by a start condition. read: 0: no stop condition detected. 1: stop condition detected (if in slave mode) or pending (if in master mode). bit 3: ackrq: smbus ac knowledge request this read-only bit is set to logic ?1? when th e smbus has received a byte and needs the ack bit to be written with the correct ack response value. bit 2: arblost: smbus ar bitration lost indicator. this read-only bit is set to lo gic ?1? when the smbus loses ar bitration while operating as a transmitter. a lost arbitration while a slave indicates a bus error condition. bit 1: ack: smbus acknowledge flag. this bit defines the out-going ack level and re cords incoming ack leve ls. it should be writ- ten each time a byte is rece ived (when ackrq=1), or read after each byte is transmitted. 0: a "not acknowledge" has been received (if in transmitter mode) or will be transmitted (if in receiver mode). 1: an "acknowledge" has been re ceived (if in transmitter mode) or will be transmitted (if in receiver mode). bit 0: si: smbus interrupt flag. this bit is set by hardware under the conditions listed in table 18.3. si must be cleared by software. while si is set, scl is held low and the smbus is stalled. sfr page: sfr address: all pages 0xc0 (bit addressable) r r r/w r/w r r r/w r/w reset value master txmode sta sto ackrq arblost ack si 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 table 18.3. sources for hardware cha nges to smb0cn ? a start is generated. ? a st op is generated. ? ar bitration is lost. ? st art is generated. ? sm b0dat is written before the start of an smbus frame. ? a st art is detected. ? ar bitration is lost. ? smb 0dat is not written before the start of an smbus frame. ? a st art followed by an address byte is received. ? m ust be cleared by software. ? a stop is detected while addressed as a slave. ? ar bitration is lost due to a detected stop. ? a pe nding stop is generated. ? a byte ha s been received and an ack response value is needed. ? af ter each ack cycle. ? a repeated start is detected as a master when sta is low (unwanted repeated start). ? scl is sensed low while attempting to gener - ate a stop or repeated start condition. ? s da is sensed low while transmitting a ?1? (excluding ack bits). ? each time si is clea red. ? the incoming ack value is low (acknowledge). ? the incoming ack value is high (not acknowledge). ? a st art has been generated. ? l ost arbitration. ? a byte ha s been transmitted and an ack/nack received. ? a byte ha s been received. ? a st art or repeated start followed by a slave address + r/w has been received. ? a stop has been received. ? m ust be cleared by software. rev. 1.0 211 c8051f360/1/2/3/4/5/6/7/8/9 bit set by hardware when: cleared by hardware when: master txmode sta sto ackrq arblost ack si c8051f360/1/2/3/4/5/6/7/8/9 212 rev. 1.0 18.4.3. data register the smbus data register smb0dat holds a byte of serial data to be transmitted or one that has just been received. software may safely read or write to the data register when the si flag is set. software should not attempt to access the smb0dat register when the smbus is enabled and the si flag is cleared to logic ?0?, as the interface may be in the process of shifting a byte of data into or out of the register. data in smb0dat is always shifted ou t msb first. after a byte has been received, the first bit of received data is located at the msb of smb0dat. while data is being shifted out, data on the bus is simultaneously being shifted in. smb0dat always contains the last data byte present on the bus. in the event of lost arbi - tration, the transition from master transmitter to slave r eceiver is made with the correct data or address in smb0dat. sfr definition 18.3. smb0dat: smbus data bits 7?0: smb0dat: smbus data. the smb0dat register contains a byte of data to be transmitted on the smbus serial inter- face or a byte that has just been received on the smbus serial interface. the cpu can read from or write to this register whenever the si serial interrupt flag (smb0cn.0) is set to logic ?1?. the serial data in the register remains stable as long as the si flag is set. when the si flag is not set, the system may be in the process of shifting data in/out and the cpu should not atte mpt to access this register. sfr page: sfr address: all pages 0xc2 r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rev. 1.0 213 c8051f360/1/2/3/4/5/6/7/8/9 18.5. smbus transfer modes the smbus interface may be configured to operate as master and/or slave. at any particular time, it will be operating in one of the following four modes: master transmitter, master receiver, slave transmitter, or slave receiver. the smbus interface enters master mo de any time a start is generated, and remains in master mode until it loses an arbitration or generates a stop. an smbus interrupt is generated at the end of all smbus byte frames; however, note that the inte rrupt is generated before the ack cycle when operat - ing as a receiver, and after the ack cycle when operating as a transmitter. 18.5.1. master transmitter mode serial data is transmitted on sda while the serial cl ock is output on scl. the smbus interface generates the start condition and transmits the first byte cont aining the address of the target slave and the data direction bit. in this case the da ta direction bit (r/w) will be logic ?0? (write). the master then transmits one or more bytes of serial data. after each byte is transmitted, an acknowled ge bit is generated by the slave. the transfer is en ded when the sto bit is set and a stop is generated. note that the interface will switch to master receiver mode if smb0dat is not written follo wing a master transmitter interrupt. figure 18.5 shows a typical master transmitter sequence. two transmit data bytes are shown, though any number of bytes may be transmitted. notice that the ?data byte transferred? interrupts occur af ter the ack cycle in this mode. a a a s w p data byte data byte sla s = start p = stop a = ack w = write sla = slave address received by smbus interface transmitted by smbus interface interrupt interrupt interrupt interrupt figure 18.5. typical mast er transmitter sequence c8051f360/1/2/3/4/5/6/7/8/9 214 rev. 1.0 18.5.2. master receiver mode serial data is received on sda while the serial clock is output on scl. the smbus interface generates the start condition and transmits the first byte containing the address of the target slave and the data direc - tion bit. in this case the data direction bit (r/w) will be logic ?1? (read). serial data is then received from the slave on sda while the smbus outputs the serial cloc k. the slave transmits one or more bytes of serial data. after each byte is received, ackrq is set to ?1? and an interrupt is generated. software must write the ack bit (smb0cn.1) to define the outgoing ackno wledge value (note: writing a ?1? to the ack bit gen - erates an ack; writing a ?0? genera tes a nack). sof tware should write a ?0? to the ack bit after the last byte is received, to transmit a na ck. the interface exits master receiver mode after the sto bit is set and a stop is generated. the in terface will switch to master transmitter mode if smb0dat is written while an active master receiver. figure 18.6 shows a typical master receiver se quence. two received data bytes are shown, though any number of bytes may be received. notice that the ?data byte transferred? interrupts oc cur before the ack cycle in this mode. data byte data byte a n a s r p sla s = start p = stop a = ack n = nack r = read sla = slave address received by smbus interface transmitted by smbus interface interrupt interrupt interrupt interrupt figure 18.6. typical m aster receiver sequence rev. 1.0 215 c8051f360/1/2/3/4/5/6/7/8/9 18.5.3. slave receiver mode serial data is received on sda and the clock is re ceived on scl. when slave events are enabled (inh = 0), the interface enters slave receiver mode when a start followed by a slave address and direction bit (write in this case) is received. upon entering slave receiver mode, an interrupt is generated and the ackrq bit is set. software responds to the received slave address with an ack, or ignores the received slave address with a nack. if the rece ived slave address is ignored, slav e interrupts will be inhibited until the next start is detected. if the received slave addr ess is acknowledged, zero or more data bytes are received. software must write the ack bit after each received byte to ack or nack the received byte. the interface exits slave receiver mode after receiving a stop. note that the interface will switch to slave transmitter mode if smb0 dat is written while an active slave receiver. figure 18.7 shows a typical slave receiver sequence. two received data bytes are shown, tho ugh any number of bytes may be received. notice that the ?data byte transferred? interrupts occur before the ack cycle in this mode. p w sla s data byte data byte a a a s = start p = stop a = ack w = write sla = slave address received by smbus interface transmitted by smbus interface interrupt interrupt interrupt interrupt figure 18.7. typical sl ave receiver sequence c8051f360/1/2/3/4/5/6/7/8/9 216 rev. 1.0 18.5.4. slave transmitter mode serial data is transmitted on sda and the clock is re ceived on scl. when slave events are enabled (inh = 0), the interface enters slave receiver mode (to re ceive the slave address) when a start followed by a slave address and direction bit (read in this case) is received. upon entering slave transmitter mode, an interrupt is generated and the ackr q bit is set. software responds to the received slave address with an ack, or ignores the received slave address with a nack. if the received slave address is ignored, slave interrupts will be inhibited un til a start is detected. if the received slave address is acknowledged, data should be written to smb0dat to be transmitted. the interface enters slave transmitter mode, and trans - mits one or more bytes of data. after each byte is tr an smitted, the master sends an acknowledge bit; if the acknowledge bit is an ack, smb0dat should be writt en with the next data byte. if the acknowledge bit is a nack, smb0dat should not be written to before si is cleared (note: an error condition may be gener - ated if smb0dat is written following a received nack whi le in slave transmitter mode). the interface exits slave transmitter mode after receiving a stop. note that the interface will sw itch to slave receiver mode if smb0dat is not written fo llowing a slave tran smitter interrupt. figure 18.8 shows a typical slave transmitter sequence. two transmitted data bytes ar e shown , though any number of bytes may be trans - mitted. notice that the ?data byte tr ansferred? interrupts occur after the ack cycle in this mode. p r sla s data byte data byte a n a s = start p = stop n = nack r = read sla = slave address received by smbus interface transmitted by smbus interface interrupt interrupt interrupt interrupt figure 18.8. typical sl ave transmitter sequence rev. 1.0 217 c8051f360/1/2/3/4/5/6/7/8/9 18.6. smbus status decoding the current smbus status can be easily decoded using the smb0cn register. in the table below, status vector refers to the four upper bits of smb0 cn: master, txmode, sta, and sto. the shown response options are only the typica l responses; application-specific procedures are allowed as long as they conform to the smbus specification. highlighted responses are allowed but do not conform to the smbus specification. table 18.4. smbus status decoding mode values read current smbus state typical response options values wr itten status vector ackrq arblost ack sta sto ack master transmitter 1110 0 0 x a master start was generated. load slave address + r/w into smb0da t. 0 0 x 1100 000 a master data or address byte was trans mitted; nack received. set sta to restart transfer. 1 0 x abort transfer. 0 1 x 001 a master data or address byte was trans mitted; ack received. load next data byte into smb0da t. 0 0 x end transfer with stop. 0 1 x end transfer with stop and st art another transfer. 1 1 x send repeated start. 1 0 x switch to master receiver mode (clear si without writ - ing new data to smb0dat). 0 0 x c8051f360/1/2/3/4/5/6/7/8/9 218 rev. 1.0 master receiver 1000 1 0 x a master data byte was received; ack requested. acknowledge received byte; read smb0da t. 0 0 1 send nack to indicate last b yte, and send stop. 0 1 0 send nack to indicate last byte, and send stop fol - lowed by start. 1 1 0 send ack followed by re peated start. 1 0 1 send nack to indicate last byte, a nd send repeated start. 1 0 0 send ack and switch to master transmitter mode (write to smb0dat before clearing si). 0 0 1 send nack and switch to master transmitter mode (write to smb0dat before clearing si). 0 0 0 slave transmitter 0100 000 a slave byte was transmitted; nac k received. no action required (expect - ing stop condition). 0 0 x 001 a slave byte was transmitted; ack received. load smb0dat with next dat a byte to transmit. 0 0 x 01x a slave byte was transmitted; er ror detected. no action required (expect - ing master to end transfer). 0 0 x 0101 0 x x a stop was detected while an ad dressed slave transmitter. no action required (transfer complete). 0 0 x table 18.4. smbus status decoding (continued) mode values read current smbus state typical response options values written status vector ackrq arblost ack sta sto ack rev. 1.0 219 c8051f360/1/2/3/4/5/6/7/8/9 slave receiver 0010 10x a slave address was received; ack requested. acknowledge received ad dress. 0 0 1 do not acknowledge re ceived address. 0 0 0 11x lost arbitration as master; slave ad dress received; ack requested. acknowledge received ad dress. 0 0 1 do not acknowledge re ceived address. 0 0 0 reschedule failed transfer; do not acknowledge received address. 1 0 0 01x lost arbitration while attempting a r epeated start. abort failed transfer. 0 0 x reschedule failed transfer. 1 0 x 0001 11 x lost arbitration while attempting a st op. no action required (transfer comp lete/aborted). 0 0 0 00x a stop was detected while an ad dressed slave receiver. no action required (transfer complete). 0 0 x 01x lost arbitration due to a detected st op. abort transfer. 0 0 x reschedule failed transfer. 1 0 x 0000 10 x a slave byte was received; ack r equested. acknowledge received byte; read smb0da t. 0 0 1 do not acknowledge re ceived byte. 0 0 0 11x lost arbitration while transmitting a da ta byte as master. abort failed transfer. 0 0 0 reschedule failed transfer. 1 0 0 table 18.4. smbus status decoding (continued) mode values read current smbus state typical response options values written status vector ackrq arblost ack sta sto ack c8051f360/1/2/3/4/5/6/7/8/9 220 rev. 1.0 19. uart0 uart0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 uart. enh anced baud rate support allows a wide range of clock sources to generate standard baud rates (details in section ?19.1. enhanced baud rate generation? on page 221 ). received data buffering allows uart0 to start reception of a second incoming data byte be fore software has finished reading the previous data byte. uart0 has two associated sfrs: serial control regist er 0 (scon0) and serial data buffer 0 (sbuf0). the single sbuf0 location provides access to both transmit and receive registers. writes to sbuf0 always access the transmit register. reads of sbuf0 always access the buffered receive register; it is not possible to read data from the transmit register. with uart0 interrupts enabled, an interrupt is generated each time a transmit is completed (ti0 is set in scon0) , or a data byte has been received (ri0 is set in scon0). the uart0 interrupt flags are not cleared by hardware when the cpu vectors to the interr upt service routine. they must be cleared manually by software, allowing software to determine the cause of the uart0 interrupt (transmit complete or receive complete). uart baud rate generator ri scon ri ti rb8 tb8 ren mce smode tx control tx clock send sbuf (tx shift) start data write to sbuf crossbar tx shift zero detector tx irq set qd clr stop bit tb8 sfr bus serial port interrupt ti port i/o rx control start rx clock load sbuf shift 0x1ff rb8 rx irq input shift register (9 bits) load sbuf read sbuf sfr bus crossbar rx sbuf (rx latch) figure 19.1. uart0 block diagram rev. 1.0 221 c8051f360/1/2/3/4/5/6/7/8/9 19.1. enhanced baud rate generation the uart0 baud rate is generated by timer 1 in 8-bit auto-reload mode. the tx clock is generated by tl 1; the rx clock is generated by a copy of tl1 (shown as rx timer in figure 19.2 ), which is not user- accessible. both tx and rx timer overflows are divid ed b y two to generate the tx and rx baud rates. the rx timer runs when timer 1 is enabled, and uses the same reload value (th1). however, an rx timer reload is forced when a start condition is de t ected on the rx pin. th is allows a receive to begin any time a start is detected, independent of the tx timer state. rx timer start detected overflow overflow th1 tl1 tx clock 2 rx clock 2 timer 1 uart figure 19.2. uart0 baud rate logic timer 1 should be configured for mode 2, 8-bit auto-reload (see section ?21.1.3. mode 2: 8-bit counter/timer with auto-reload? on page 249 ). the timer 1 reload value should be set so that overflows will occur at two times the desired uart ba ud rate frequenc y. note that timer 1 may be clocked by one of six sources: sysclk, sysclk / 4, sysclk / 12, sysclk / 48, the external oscillator clock / 8, or an ex ternal input t1. for any given timer 1 clock source, the uart0 baud rate is determined by equation 19.1 -a and equation 19.1 -b. uartbaudrate 1 2 -- - t1_overflow_rate = t1_overflow_rate t1 clk 256 th1 ? ------------------------- - = a) b) equation 19.1. uart0 baud rate where t1 clk is the frequency of the clock supplied to timer 1, and t1h is the high byte of timer 1 (reload value). timer 1 clock frequency is selected as described in section ?21. timers? on page 247 . a quick ref - erence for typical baud rates and syst em clo ck frequencies is given in ta b l e 19.1 through ta b l e 19.6 . note that the internal oscillator may still generate the system clock when the ex ternal oscillator is driving timer 1. c8051f360/1/2/3/4/5/6/7/8/9 222 rev. 1.0 19.2. operational modes uart0 provides standard asynchronous, full duplex communication. the uart mode (8-bit or 9-bit) is selected by the s0mode bit (scon0.7). typical uart connection options are shown below. or rs-232 c8051fxxx rs-232 level xltr tx rx c8051fxxx rx tx mcu rx tx figure 19.3. uart interconnect diagram 19.2.1. 8-bit uart 8-bit uart mode uses a total of 10 bits per data byte: one start bit, eight data bits (lsb first), and one stop bit . data are transmitted lsb first from the tx0 pin a nd received at the rx0 pin. on receive, the eight data bits are stored in sbuf0 and the stop bit goes into rb80 (scon0.2). data transmission begins wh en s oftware writes a data byte to th e sbuf0 register. the ti0 transmit inter - rupt flag (scon0.1) is set at the end of the transmi ssion ( the beginning of the stop-bit time). data recep - tion can begin any time after the ren0 rece iv e enable bit (scon0.4) is set to logic ?1?. after the stop bit is received, the dat a byte w ill be loaded into the sbuf0 re ceive register if the follo wing conditions are met: ri0 must be logic ?0?, and if mce0 is logic ?1?, the stop bit must be logic ?1?. in the event of a receive data ov errun, the first received 8 bits are latched into the sbuf0 receive register and the following overrun data b its are lost. if these conditions are met, the eight bits of data is stor ed in sbuf0, the stop bit is stored in rb80 and the ri0 flag is set. if these conditio ns are not met, sbuf0 and rb80 will no t be loaded and the ri0 flag will not be set. an interrupt will occur if enabled when ei ther ti0 or ri0 is set. d1 d0 d2 d3 d4 d5 d6 d7 start bit mark stop bit bit times bit sampling space figure 19.4. 8-bit u art timing diagram rev. 1.0 223 c8051f360/1/2/3/4/5/6/7/8/9 19.2.2. 9-bit uart 9-bit uart mode uses a total of eleven bits per data byte: a start bit, 8 data bits (lsb first), a programma - ble ninth data bit, and a stop bit. the state of the nint h transmit dat a bit is determ ined by the value in tb80 (scon0.3), which is assigned by user software. it can be assigned the value of the parity flag (bit p in reg - ister psw) for error detection, or used in multiprocessor communications. on receive, the ninth data bit g oes into rb80 (scon0.2) and the stop bit is ignored. data transmission begins when an instruction writes a d ata byte to the sbuf0 register. the ti0 transmit interrupt flag (scon0.1) is set at the end of the tran smission (the beginning of the stop-bit time). data reception can begin any time after the ren0 receive en able bit (scon0.4) is set to ?1?. after the stop bit is received, the data byte will be lo aded into the sbuf0 receive register if the followin g conditions are met: (1) ri0 must be logic ?0?, and (2) if mce0 is logic ?1?, the 9th bit must be logic ?1? (when mce0 is logic ?0?, the state of the ninth data bit is unimportant). if these conditions are met, the eight bits of data are stored in sbuf0, the ninth bit is stored in rb80, and the ri0 flag is set to ?1?. if the above conditions are not met, sbuf0 and rb80 will not be loaded and the ri0 flag will not be set to ?1?. a ua rt0 interrupt will occur if enabled when either ti0 or ri0 is set to ?1?. d1 d0 d2 d3 d4 d5 d6 d7 start bit mark stop bit bit times bit sampling space d8 figure 19.5. 9-bit u art timing diagram c8051f360/1/2/3/4/5/6/7/8/9 224 rev. 1.0 19.3. multiprocessor communications 9-bit uart mode supports multiprocessor communication between a master processor and one or more slave processors by special use of t he ninth data bit. when a master processor wants to transmit to one or more slaves, it first sends an address byte to select th e target(s). an address byte differs from a data byte in that its ninth bit is logic ?1?; in a data byte, the nint h bit is always set to logic ?0?. setting the mce0 bit (scon0.5) of a slave processor co n figures its uart such that when a stop bit is received, the uart will genera te an interrupt only if the ninth bit is logic ?1? (rb80 = 1) signifying an address byte has been rece ived. in the uart interrupt handler, software will compare the received address with the slave's own assigned 8-bit address. if the addresses ma tch, the slave will clear its mce0 bit to enable interrupts on the reception of the followi ng data byte(s). slaves that weren't addressed leave their mce0 bits set and do not generate interrupts on the reception of the following data bytes, thereby ignoring the data. once the entire message is received, the addressed slave resets its mce0 bit to ignore all transmissions until it receives the next address byte. multiple addresses can be assigned to a single sl ave and /or a single address can be assigned to multiple slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. the master processor can be configured to receive all transmissi ons or a protocol can be implemented such that the master/slave role is tem porarily reversed to enable half-duplex transmission between the original master and slave(s). master device slave device tx rx rx tx slave device rx tx slave device rx tx v+ figure 19.6. uart multi-processor mode interconnect diagram rev. 1.0 225 c8051f360/1/2/3/4/5/6/7/8/9 sfr definition 19.1. scon0: serial port 0 control bit 7: s0mode: serial port 0 operation mode. this bit selects the uart0 operation mode. 0: 8-bit uart with variable baud rate. 1: 9-bit uart with variable baud rate. bit 6: unused. read = 1b. write = don?t care. bit 5: mce0: multiprocessor communication enable. the function of this bit is dependent on the serial port 0 operation mode. s0mode = 0: checks for valid stop bit. 0: logic level of stop bit is ignored. 1: ri0 will only be activated if stop bit is logic level ?1?. s0mode = 1: multiprocesso r communications enable. 0: logic level of ninth bit is ignored. 1: ri0 is set and an interrupt is generated only when the ninth bit is logic ?1?. bit 4: ren0: receive enable. this bit enables/disables the uart receiver. 0: uart0 reception disabled. 1: uart0 reception enabled. bit 3: tb80: ninth transmission bit. the logic level of this bit will be assigned to the ninth transmission bit in 9-bit uart mode. it is not used in 8-bit uart mode. set or cleared by software as required. bit 2: rb80: ninth receive bit. rb80 is assigned the value of the stop bit in mode 0; it is assigned the value of the 9th data bit in mode 1. bit 1: ti0: transmit interrupt flag. set by hardware when a byte of data has been transmitted by uart0 (after the 8th bit in 8- bit uart mode, or at the beginning of the stop bit in 9-bit uart mode). when the uart0 interrupt is enabled, setting this bit causes the cpu to vector to the uart0 interrupt service routine. this bit must be cleared manually by software. bit 0: ri0: receive interrupt flag. set to ?1? by hardware when a byte of data has been received by uart0 (set at the stop bit sampling time). when the uart0 interrupt is enab led, setting this bit to ?1? causes the cpu to vector to the uart0 interrup t service routine. this bit must be cleared manually by soft- ware. sfr page: sfr address: all pages 0x98 (bit addressable) r/w r r/w r/w r/w r/w r/w r/w reset value s0mode ? mce0 ren0 tb80 rb80 ti0 ri0 01000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 c8051f360/1/2/3/4/5/6/7/8/9 226 rev. 1.0 sfr definition 19.2. sbuf0: serial (uart0 ) por t data buffer bits 7 ? 0: sbuf0[7:0]: serial data buffer bits 7 ? 0 (msb ? lsb) this sfr accesses two registers; a transmit shif t register and a receive latch register. when data is written to sbuf0, it goes to the transmit shift register and is he ld for serial transmis- sion. writing a byte to sbuf0 initiates the transmission. a read of sbuf0 returns the con- tents of the receive latch. sfr page: sfr address: all pages 0x99 r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 table 19.1. timer settings for standard baud rates using the internal 24.5 mhz oscillator sysclk from internal osc. notes: 1. sca1 ? sca0 and t1m bit definitions can be found in section 21.1 . 2. x = don? t care. rev. 1.0 227 c8051f360/1/2/3/4/5/6/7/8/9 frequency: 24.5 mhz target baud rate (bps) baud rate % error oscilla- tor divide factor timer clock source sca1?sca0 (pre-scale select) 1 t1m 1 timer 1 reload value (hex) 230400 ?0.32% 106 sysclk xx 2 1 0xcb 115200 ?0.32% 212 sysclk xx 1 0x96 57600 0.15% 426 sysclk xx 1 0x2b 28800 ?0.32% 848 sysclk/4 01 0 0x96 14400 0.15% 1704 sysclk/12 00 0 0xb9 9600 ?0.32% 2544 sysclk/12 00 0 0x96 2400 ?0.32% 10176 sysclk/48 10 0 0x96 1200 0.15% 20448 sysclk/48 10 0 0x2b table 19.2. timer settings for standard baud rates u sing an external 25.0 mhz oscillator sysclk and timer clock from external osc. sysclk from internal osc., timer clock from external osc. notes: 1. sca1 ? sca0 and t1m bit definitions can be found in section 21.1 . 2. x = don?t care. c8051f360/1/2/3/4/5/6/7/8/9 228 rev. 1.0 frequency: 25.0 mhz target baud rate (bps) baud rate % error oscilla- tor divide factor timer clock source sca1?sca0 (pre-scale select) 1 t1m 1 timer 1 reload value (hex) 230400 ?0.47% 108 sysclk xx 2 1 0xca 115200 0.45% 218 sysclk xx 1 0x93 57600 ?0.01% 434 sysclk xx 1 0x27 28800 0.45% 872 sysclk/4 01 0 0x93 14400 ?0.01% 1736 sysclk/4 01 0 0x27 9600 0.15% 2608 extclk/8 11 0 0x5d 2400 0.45% 10464 sysclk/48 10 0 0x93 1200 ?0.01% 20832 sysclk/48 10 0 0x27 57600 ?0.47% 432 extclk/8 11 0 0xe5 28 800 ?0.47% 864 extclk/8 11 0 0xca 14400 0.45% 1744 extclk/8 11 0 0x93 9600 0.15% 2608 extclk/8 11 0 0x5d table 19.3. timer settings for standard baud rates using an external 22.1 184 mhz oscillator sysclk and timer clock from external osc. sysclk from internal osc., timer clock from external osc. notes: 1. sca1 ? sca0 and t1m bit definitions can be found in section 21.1 . 2. x = don?t care. rev. 1.0 229 c8051f360/1/2/3/4/5/6/7/8/9 frequency: 22.1184 mhz target baud rate (bps) baud rate % error oscilla- tor divide factor timer clock source sca1?sca0 (pre-scale select) 1 t1m 1 timer 1 reload value (hex) 230400 0.00% 96 sysclk xx 2 1 0xd0 115200 0.00% 192 sysclk xx 1 0xa0 57600 0.00% 384 sysclk xx 1 0x40 28800 0.00% 768 sysclk/12 00 0 0xe0 14400 0.00% 1536 sysclk/12 00 0 0xc0 9600 0.00% 2304 sysclk/12 00 0 0xa0 2400 0.00% 9216 sysclk/48 10 0 0xa0 1200 0.00% 18432 sysclk/48 10 0 0x40 230400 0.00% 96 extclk/8 11 0 0xfa 1 15200 0.00% 192 extclk/8 11 0 0xf4 57600 0.00% 384 extclk/8 11 0 0xe8 28800 0.00% 768 extclk/8 11 0 0xd0 14400 0.00% 1536 extclk/8 11 0 0xa0 9600 0.00% 2304 extclk/8 11 0 0x70 table 19.4. timer settings for standard baud rates using an external 18.432 mhz oscillator sysclk and timer clock from external osc. sysclk from internal osc., timer clock from external osc. notes: 1. sca1 ? sca0 and t1m bit definitions can be found in section 21.1 . 2. x = don? t care. c8051f360/1/2/3/4/5/6/7/8/9 230 rev. 1.0 frequency: 18.432 mhz target baud rate (bps) baud rate % error oscilla- tor divide factor timer clock source sca1?sca0 (pre-scale select) 1 t1m 1 timer 1 reload value (hex) 230400 0.00% 80 sysclk xx 2 1 0xd8 115200 0.00% 160 sysclk xx 1 0xb0 57600 0.00% 320 sysclk xx 1 0x60 28800 0.00% 640 sysclk/4 01 0 0xb0 14400 0.00% 1280 sysclk/4 01 0 0x60 9600 0.00% 1920 sysclk/12 00 0 0xb0 2400 0.00% 7680 sysclk/48 10 0 0xb0 1200 0.00% 15360 sysclk/48 10 0 0x60 230400 0.00% 80 extclk/8 11 0 0xfb 1 15200 0.00% 160 extclk/8 11 0 0xf6 57600 0.00% 320 extclk/8 11 0 0xec 28800 0.00% 640 extclk/8 11 0 0xd8 14400 0.00% 1280 extclk/8 11 0 0xb0 9600 0.00% 1920 extclk/8 11 0 0x88 table 19.5. timer settings for standard baud rates using an external 1 1.0592 mhz oscillator sysclk and timer clock from external osc. sysclk from internal osc., timer clock from external osc. notes: 1. sca1 ? sca0 and t1m bit definitions can be found in section 21.1 . 2. x = don?t care. rev. 1.0 231 c8051f360/1/2/3/4/5/6/7/8/9 frequency: 11.0592 mhz target baud rate (bps) baud rate % error oscilla- tor divide factor timer clock source sca1?sca0 (pre-scale select) 1 t1m 1 timer 1 reload value (hex) 230400 0.00% 48 sysclk xx 2 1 0xe8 115200 0.00% 96 sysclk xx 1 0xd0 57600 0.00% 192 sysclk xx 1 0xa0 28800 0.00% 384 sysclk xx 1 0x40 14400 0.00% 768 sysclk/12 00 0 0xe0 9600 0.00% 1152 sysclk/12 00 0 0xd0 2400 0.00% 4608 sysclk/12 00 0 0x40 1200 0.00% 9216 sysclk/48 10 0 0xa0 230400 0.00% 48 extclk/8 11 0 0xfd 1 15200 0.00% 96 extclk/8 11 0 0xfa 57600 0.00% 192 extclk/8 11 0 0xf4 28800 0.00% 384 extclk/8 11 0 0xe8 14400 0.00% 768 extclk/8 11 0 0xd0 9600 0.00% 1152 extclk/8 11 0 0xb8 table 19.6. timer settings for standard baud rates using an external 3.6864 mhz oscillator sysclk and timer clock from external osc. sysclk from internal osc., timer clock from external osc. notes: 1. sca1 ? sca0 and t1m bit definitions can be found in section 21.1 . 2. x = don? t care. c8051f360/1/2/3/4/5/6/7/8/9 232 rev. 1.0 frequency: 3.6864 mhz target baud rate (bps) baud rate% error oscilla- tor divide factor timer clock source sca1?sca0 (pre-scale select) 1 t1m 1 timer 1 reload value (hex) 230400 0.00% 16 sysclk xx 2 10xf8 115200 0.00% 32 sysclk xx 1 0xf0 57600 0.00% 64 sysclk xx 1 0xe0 28800 0.00% 128 sysclk xx 1 0xc0 14400 0.00% 256 sysclk xx 1 0x80 9600 0.00% 384 sysclk xx 1 0x40 2400 0.00% 1536 sysclk/12 00 0 0xc0 1200 0.00% 3072 sysclk/12 00 0 0x80 230400 0.00% 16 extclk/8 11 0 0xff 1 15200 0.00% 32 extclk/8 11 0 0xfe 57600 0.00% 64 extclk/8 11 0 0xfc 28800 0.00% 128 extclk/8 11 0 0xf8 14400 0.00% 256 extclk/8 11 0 0xf0 9600 0.00% 384 extclk/8 11 0 0xe8 table 19.7. timer settings for standard baud rates using the pll notes: 1. sca1 ? sca0 and t1m bit definitions can be found in section 21.1 . 2. x = don?t care. rev. 1.0 233 c8051f360/1/2/3/4/5/6/7/8/9 table 19.8. timer settings for standard baud rates using the pll notes: 1. sca1 ? sca0 and t1m bit definitions can be found in section 21.1 . 2. x = don?t care. frequency: 50.0 mhz target baud rate (bps) baud rate % error oscilla- tor divide factor timer clock source sca1-sca0 (pre-scale select) 1 t1m 1 timer 1 reload value (hex) 230400 0.45% 218 sysclk xx 2 1 0x93 115200 ?0.01% 434 sysclk xx 1 0x27 57600 0.45% 872 sysclk/4 01 0 0x93 28800 ?0.01% 1736 sysclk/4 01 0 0x27 14400 0.22% 3480 sysclk/12 00 0 0x6f 9600 ?0.01% 5208 sysclk/12 00 0 0x27 2400 ?0.01% 20832 sysclk/48 10 0 0x27 frequency: 100.0 mhz target baud rate (bps) baud rate % error oscilla- tor divide factor timer clock source sca1-sca0 (pre-scale select) 1 t1m 1 timer 1 reload value (hex) 230400 ?0.01% 434 sysclk xx 2 1 0x27 115200 0.45% 872 sysclk/4 01 0 0x93 57600 ?0.01% 1736 sysclk/4 01 0 0x27 28800 0.22% 3480 sysclk/12 00 0 0x6f 14400 ?0.47% 6912 sysclk/48 10 0 0xb8 9600 0.45% 10464 sysclk/48 10 0 0x93 c8051f360/1/2/3/4/5/6/7/8/9 234 rev. 1.0 20. enhanced serial peri pheral interface (spi0) the enhanced serial peripheral interface (spi0) prov ides access to a flexible, full-duplex synchronous serial bus. spi0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports mul - tiple masters and slaves on a single spi b us. the slave-select (nss) signal can be configured as an input to select spi0 in slave mode, or to disable master mode operation in a multi-master environment, avoiding contention on the spi bus when more than one master attempts simultaneous data transfers. nss can also be configured as a chip-select output in master mode, or disabled for 3-wire operation. additional gen - eral purpose port i/o pins can be used to se lec t multiple slave dev ices in master mode. sfr bus data path control sfr bus write spi0dat receive data buffer spi0dat 0 1 2 3 4 5 6 7 shift register spi control logic spi0ckr scr7 scr6 scr5 scr4 scr3 scr2 scr1 scr0 spi0cfg spi0cn pin interface control pin control logic c r o s s b a r port i/o read spi0dat spi irq tx data rx data sck mosi miso nss transmit data buffer clock divide logic sysclk ckpha ckpol slvsel nssmd1 nssmd0 spibsy msten nssin srmt rxbmt spif wcol modf rxovrn txbmt spien figure 20.1. spi block diagram rev. 1.0 235 c8051f360/1/2/3/4/5/6/7/8/9 20.1. signal descriptions the four signals used by spi0 (mosi, miso, sck, nss) are described below. 20.1.1. master out, slave in (mosi) the master-out, slave-in (mosi) signal is an output fr om a master device and an input to slave devices. it is used to serially transfer data from the master to th e slave. this signal is an output when spi0 is operat - ing as a master and an input when spi0 is operating as a slave. data is transferred most-significant bit first. when configured as a master, mosi is driven by the msb of the shift register in both 3- and 4-wire mode. 20.1.2. master in, slave out (miso) the master-in, slave-out (miso) signal is an output from a slave device and an input to the master device. it is used to serially transfer data from the slave to the master. this signal is an input when spi0 is operat - ing as a master and an output when spi0 is operating a s a slave. data is transferred most-significant bit first. the miso pin is placed in a high-impedance stat e when the spi module is disabled and when the spi operates in 4-wire mode as a slave that is not select ed. when acting as a slave in 3-wire mode, miso is always driven by the msb of the shift register. 20.1.3. serial clock (sck) the serial clock (sck) signal is an output from the mast er device and an input to slave devices. it is used to synchronize the transfer of data between the mast er and slave on the mosi and miso lines. spi0 gen - erates this signal when operating as a master. the sck signal is ignored by a spi slave when the slave is n ot selected (nss = 1) in 4-wire slave mode. 20.1.4. slave select (nss) the function of the slave-select (nss) signal is dependent on the setting of the nssmd1 and nssmd0 bits in the spi0cn register. there are three possib le modes that can be selected with these bits: 1. nssmd[1:0] = 00: 3-wire master or 3-wire slave mode: spi0 operates in 3-wire mode, and nss is disabled. when operating as a slave dev ice, spi0 is always selected in 3-wire mode. since no select signal is present, spi0 must be the only slave on the bus in 3-wire mode. this is intended for point-to-point communica tion between a master and one slave. 2. nssmd[1:0] = 01: 4-wire slave or multi-ma ster mode: spi0 operates in 4-wire mode, and nss is enabled as an input. when operating as a slave, nss selects the spi0 device. when operating as a master, a 1-to-0 transition of th e nss signal disables t he master function of spi0 so that multiple master devices can be used on the same spi bus. 3. nssmd[1:0] = 1x: 4-wire master mode: spi0 oper ates in 4-wire mode, and nss is enabled as an output. the setting of nssm d0 determines what logic leve l the nss pin will output. this configuration should only be used wh en operating spi0 as a master device. see figure 20.2, figure 20.3, and figure 20.4 for typical connection diag ram s of the various operational modes. note that the setting of nssmd bits affects the pinout of the device. when in 3-wire master or 3-wire slave mode, the nss pin will not be mapped by the crossbar. in all other modes, the nss signal will be mapped to a pin on the device. see section ?17. port input/output? on page 183 for general purpose port i/o and crossbar information. c8051f360/1/2/3/4/5/6/7/8/9 236 rev. 1.0 20.2. spi0 master mode operation a spi master device initiates all data transfers on a spi bus. spi0 is placed in master mode by setting the master enable flag (msten, spi0cn.6). writing a byte of data to the spi0 data register (spi0dat) when in master mode writes to the transmit buffer. if the spi shift register is empty, the byte in the transmit buffer is moved to the shift register, and a data transfer begins. the spi0 master immediately shifts out the data serially on the mosi line while provid ing the serial clock on sck. the spi f (spi0cn.7) flag is set to logic ?1? at the end of the transfer. if interrupts are enabled, an interrupt request is generated when the spif flag is set. while the spi0 master transf ers data to a slave on the mosi line, the addressed spi slave device simultaneously transfers the contents of its shift register to the spi master on the miso line in a full-duplex operation. therefore, the spif flag serves as both a transmit-complete and receive-data-ready flag. the data byte received from the slave is transferred msb-fi rst into the master's shift register. when a byte is fully shifted into the register, it is moved to the receive buffer where it can be read by the processor by reading spi0dat. when configured as a master, spi0 can operate in one of thr ee different modes: multi-master mode, 3-wire single-master mode, and 4-wire single-master mode. the default, multi-master mode is active when nssmd1 (spi0cn.3) = 0 and nssmd0 (spi0cn.2) = 1. in this mode, nss is an input to the device, and is used to disable the master spi0 when another mast er is accessing the bus. when nss is pulled low in this mode, msten (spi0cn.6) and spien (spi0cn.0) are set to 0 to disable the spi master device, and a mode fault is generate d (modf, spi0cn.5 = 1). mode fault will gen erate an inte rrupt if e nabled. spi0 must be manually re-enabled in soft ware under these circumstances. in multi-master systems, devices will typically default to being slave devices while they are not acting as the system master device. in multi-mas - ter mode, slave devices can be addressed individua lly (if ne eded) using general-purpose i/o pins. figure 20.2 shows a connection diagram between two ma ster devic es in mu ltiple-master mode. 3-wire single-master mode is active when nssmd1 (s pi0cn.3) = 0 and nssmd0 ( spi0cn.2) = 0. in this mode, nss is not used, and is not mapped to an exte rnal port pin through the crossbar. any slave devices that must be addressed in this mode should be selected using general-purpose i/o pins. figure 20.3 shows a connection diagram between a master dev ice in 3- wire master mode and a slave device. 4-wire single-master mode is active when nssmd1 (spi0cn.3) = 1. in this mode, nss is configured as an output pin, and can be used as a slave-select signal for a single spi dev ice. in this mode, the output value of nss is controlled (in software) with the bit nssm d0 (spi0cn.2). additional slave devices can be addressed using general-purpose i/o pins. figure 20.4 shows a connection diagram for a master device in 4-wire master mode and two slave devices. master device 2 master device 1 mosi miso sck miso mosi sck nss gpio nss gpio slave device master device mosi miso sck miso mosi sck slave device master device mosi miso sck miso mosi sck nss nss gpio slave device mosi miso sck nss rev. 1.0 237 c8051f360/1/2/3/4/5/6/7/8/9 figure 20.2. multiple-master mode connect ion diagram figure 20.3. 3-wire single master and 3-wire single slave mode connection diagram figure 20.4. 4-wire single master mod e and 4-wire slave mode connection diagram c8051f360/1/2/3/4/5/6/7/8/9 238 rev. 1.0 20.3. spi0 slave mode operation when spi0 is enabled and not confi gured as a master, it will operate as a spi slave. as a slave, bytes are shifted in through the mosi pin a nd out through the miso pin by a ma ster device controlling the sck sig - nal. a bit counter in the spi0 logic counts sck edges. when 8 bits have been shifted through the shift reg - ister, the spif flag is set to logic ?1?, and the byte is cop ied into the receive buffer. data is read from the receive buffer by reading spi0dat. a slave device cannot initiate transfers. data to be transferred to the master device is pre-loaded into the shift register by writing to spi0dat. writes to spi0dat are double- buffered, and are placed in the transmit buffer first. if the shift register is empty, the contents of the transmit buffer will immediately be transferred into the shift register. when the sh ift register already contains data, the spi will load the shift register wi th the transmit buffer?s contents af ter the last sck edg e of the next (or current) spi transfer. when configured as a slave, spi0 can be configured fo r 4-wire or 3-wire operation. the default, 4-wire slave mode, is active when nssmd1 (spi0cn.3) = 0 and nssmd0 (spi0cn.2) = 1. in 4-wire mode, the nss signal is routed to a port pin a nd configured as a digital input. spi0 is enabled when nss is logic ?0?, and disabled when nss is logic ?1?. the bit counter is reset on a falling edge of nss. note that the nss signal must be driven low at least 2 system clocks befo re the first active edge of sck for each byte trans - fer. figure 20.4 shows a connection diagram between two sl ave d evices in 4-wire slave mode and a mas - ter device. 3-wire slave mode is active when nssmd1 (spi0cn. 3) = 0 and nssmd0 (spi0cn.2) = 0. nss is not used in this mode, and is not mapped to an external port pin through the crossbar. since there is no way of uniquely addressing the device in 3-wire slave mode , spi0 must be the only slav e device present on the bus. it is important to note that in 3-wire slave mode there is no external means of resetting the bit counter that determines when a full byte has been received. th e bit counter can only be reset by disabling and re- enabling spi0 with the spien bit. figure 20.3 shows a connection diagram between a slave device in 3- wire slave mode and a master device. 20.4. spi0 interrupt sources when spi0 interrupts are e nabled, the following four flags will gener ate an interrupt when they are set to logic ?1?: all of the following bits must be cleared by software. 1. the spi interrupt flag, spif (spi0 cn.7) is s et to logic ?1? at the end of each byte transfer. this flag can occur in all spi0 modes. 2. the write collision flag, wcol (spi0cn.6) is set to logic ?1? if a write to spi0dat is attempted when the transmit buffer has not been emptied to the spi shift register. when this occurs, the write to spi0dat w ill be ignored, and the transmit buffer will not be written.this flag can occur in all spi0 modes. 3. the mode fault flag modf (spi0cn.5) is set to logic ?1? when spi0 is configured as a mas - ter, and for multi-master mode and the nss pin is pulled low. when a mode fault occurs, the mst en and spien bits in spi0cn are set to logic ?0? to disable spi0 and allow another mas - ter device to access the bus. 4. the receive overrun flag rxovrn (spi0cn.4) is set to logic ?1? when configured as a slave, and a transfer is completed and the receive buffer still holds an unread byte from a previous transfer. the new byte is not transferred to the receive buffer, allowing the previously received data byte to be read. the data byte which caused the overrun is lost. rev. 1.0 239 c8051f360/1/2/3/4/5/6/7/8/9 20.5. serial clock timing four combinations of serial clock phase and polarity can be selected using the clock control bits in the spi0 configuration register (spi0cfg). the ckpha bit ( spi0cfg.5) selects one of two clock phases (edge used to latch the data). the ckpol bit (spi0cfg.4) selects between an active-high or active-low clock. both master and slave devices must be config ured to use the same clock phase and polarity. spi0 should be disabled (by clearing the spien bit, spi0cn.0) when changing the clock phase or polarity. the clock and data line relationships for master mode are shown in figure 20.5 . for slave mode, the clock and data relationships are shown in figure 20.6 and figure 20.7 . note that ckpha must be set to ?0? on both the master and slave spi when communicating be tween two of the following devices: c8051f04x, c8051f06x, c8051f12x, c8051f31x, c8051f32x, c8051f33x, and c8051f36x. the spi0 clock rate register (spi0c kr) as shown in sfr definition 20.3 controls the master mode serial clock frequency. this register is ignored when o perating in slave mode. when the spi is configured as a master, the maximum data transfer rate (bits/sec) is one-half the s ystem clock frequency or 12.5 mhz, whichever is slower. when the spi is configured as a sl ave, the maximum data transfer rate (bits/sec) for full-duplex operation is 1/10 the system clock frequency , provided that the master issues sck, nss (in 4- wire slave mode), and the serial input data synchrono usly with the slave?s system clock. if the master issues sck, nss, and the serial input data asynchronously, the maximum data transfer rate (bits/sec) must be less than 1/10 the system clock frequency. in the special case where the master only wants to transmit data to the slave and does not need to receive data from the slave (i.e. half-duplex operation), the spi slave can receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency. this is provided that the master i ssues sck, nss, and the serial inpu t data synchronously with the slave?s system clock. sck (ckpol=0, ckpha=0) sck (ckpol=0, ckpha=1) sck (ckpol=1, ckpha=0) sck (ckpol=1, ckpha=1) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 miso/mosi nss (must remain high in multi-master mode) figure 20.5. master mode data/clock timing msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 miso nss (4-wire mode) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mosi sck (ckpol=0, ckpha=0) sck (ckpol=1, ckpha=0) sck (ckpol=0, ckpha=1) sck (ckpol=1, ckpha=1) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 miso nss (4-wire mode) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mosi c8051f360/1/2/3/4/5/6/7/8/9 240 rev. 1.0 figure 20.6. slave mode data /clock timing (ckpha = 0) figure 20.7. slave mode data /clock timing (ckpha = 1) rev. 1.0 241 c8051f360/1/2/3/4/5/6/7/8/9 20.6. spi special function registers spi0 is accessed and controlled through four special function registers in the system controller: spi0cn control register, spi0dat data re gister, spi0cfg configuration register, and spi0ckr clock rate register. the four special function registers related to the operation of the spi0 bus are described in the following figures. sfr definition 20.1. spi0cfg: spi0 configuration bit 7: spibsy: spi busy (read only). this bit is set to logic ?1? when a spi transfer is in progress (master or slave mode). bit 6: msten: master mode enable. 0: disable master mode. operate in slave mode. 1: enable master mode. operate as a master. bit 5: ckpha: spi0 clock phase. this bit controls the spi0 clock phase. 0: data centered on first edge of sck period. * 1: data centered on second edge of sck period. * bit 4: ckpol: spi0 clock polarity. this bit controls the spi0 clock polarity. 0: sck line low in idle state. 1: sck line high in idle state. bit 3: slvsel: slave selected flag (read only). this bit is set to logic ?1? whenever the nss pin is low indicating spi0 is the selected slave. it is cleared to logic ?0? when nss is high (slave not selected). this bit does not indicate the instantaneous value at the nss pin, but ra ther a de-glitched version of the pin input. bit 2: nssin: nss instantaneous pin input (read only). this bit mimics the instantaneous value that is present on the nss port pin at the time that the register is read. this input is not de-glitched. bit 1: srmt: shift register empty (valid in slave mode, read only). this bit will be set to logic ?1? when all data has been transferred in/out of the shift register, and there is no new information available to read from the transmit buffer or write to the receive buffer. it returns to logic ?0? when a data byte is transferred to the shift register from the transmit buffer or by a transition on sck. note: srmt = 1 when in master mode. bit 0: rxbmt: receive buffer empty (valid in slave mode, read only). this bit will be set to logic ?1? when the receiv e buffer has be en read and contains no new information. if there is new information available in the receive buffer that has not been read, this bit will return to logic ?0?. note: rxbmt = 1 when in master mode. *note: in slave mode, data on mosi is sampled in the center of each data bit. in master mode, data on miso is sampled one sysclk before the end of each data bit, to provide maximum settling time for the slave device. see table 20.1 for timing parameters. sfr page: sfr address: all pages 0xa1 r r/w r/w r/w r r r r reset value spibsy msten ckpha ckpol slvsel nssin srmt rxbmt 00000111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 c8051f360/1/2/3/4/5/6/7/8/9 242 rev. 1.0 sfr definition 20.2. spi0cn: spi0 control bit 7: spif: spi0 interrupt flag. this bit is set to logic ?1? by hardware at the end of a data transfer. if interrupts are enabled, setting this bit causes the cpu to vector to the spi0 interrupt service routine. this bit is not automatically cleared by hardware. it must be cleared by software. bit 6: wcol: write collision flag. this bit is set to logic ?1? by hardware (and generates a spi0 interrupt) to indicate a write to the spi0 data register was attempted while a da ta transfer was in progress. it must be cleared by software. bit 5: modf: mode fault flag. this bit is set to logic ?1? by hardware (and generates a spi0 interrupt) when a master mode collision is detected (nss is low, msten = 1, and nssmd[1:0] = 01). this bit is not auto- matically cleared by hardware. it must be cleared by software. bit 4: rxovrn: receive overru n flag (slave mode only). this bit is set to logic ?1? by hardware (and generates a spi0 interrupt) when the receive buffer still holds unread da ta from a previous transfer and the la st bit of the curr ent transfer is shifted into the spi0 shift register. this bit is not automatically cleare d by hardware. it must be cleared by software. bits 3 ? 2: nssmd1 ? nssmd0: slave select mode. selects between the following nss operation modes: (see section 20.2 and section 20.3). 00: 3-wire slave or 3-wire master mode. nss signal is not routed to a port pin. 01: 4-wire slave or multi-master mode (defau lt). nss is always an input to the device. 1x: 4-wire single-master mode. nss signal is mapped as an ou tput from the device and will assume the value of nssmd0. bit 1: txbmt: transmit buffer empty. this bit will be set to logic ?0? when new data has been written to the transmit buffer. when data in the transmit buffer is tr ansferred to the spi sh ift register, this bit will be set to logic ?1?, indicating that it is safe to writ e a new byte to the transmit buffer. bit 0: spien: spi0 enable. this bit enables/disables the spi. 0: spi disabled. 1: spi enabled. sfr page: sfr address: all pages 0xf8 (bit addressable) r/w r/w r/w r/w r/w r/w r r/w reset value spif wcol modf rxovrn nssmd1 nssmd0 txbmt spien 00000110 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rev. 1.0 243 c8051f360/1/2/3/4/5/6/7/8/9 sfr definition 20.3. spi0ckr: spi0 clock rate bits 7 ? 0: scr7 ? scr0: spi0 clock rate. these bits determine the frequency of the sck output when the spi0 module is configured for master mode operation. the sck clock frequ ency is a divided version of the system clock, and is given in the following equation, where sysclk is the system clock frequency and spi0ckr is the 8-bit value held in the spi0ckr register. for 0 <= spi0ckr <= 255 example: if sysclk = 2 mhz and spi0ckr = 0x04, sfr page: sfr address: all pages 0xa2 r/w r/w r/w r/w r/w r/w r/w r/w reset value scr7 scr6 scr5 scr4 scr3 scr2 scr1 scr0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 f sck 2000000 241 + () f sck 200 khz = f sck sysclk 2 spi 0 ckr 1+ () sfr definition 20.4. spi0dat: spi0 data bits 7 ? 0: spi0dat: spi0 transmit and receive data. the spi0dat register is used to transmit an d receive spi0 data. writing data to spi0dat places the data into the transmit buffer and initiates a transfer when in master mode. a read of spi0dat returns the contents of the receive buffer. sfr page: sfr address: all pages 0xa3 r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sck* t mckh t mckl mosi t mis miso * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t mih sck* t mckh t mckl miso t mih mosi * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t mis c8051f360/1/2/3/4/5/6/7/8/9 244 rev. 1.0 figure 20.8. spi master timing (ckpha = 0) figure 20.9. spi master timing (ckpha = 1) sck* t se nss t ckh t ckl mosi t sis t sih miso t sd t soh * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t sez t sdz sck* t se nss t ckh t ckl mosi t sis t sih miso t sd t soh * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t slh t sez t sdz rev. 1.0 245 c8051f360/1/2/3/4/5/6/7/8/9 figure 20.10. spi slave timing (ckpha = 0) figure 20.11. spi slave timing (ckpha = 1) table 20.1. spi slave timing parameters parameter description min max units master mode timing* (se e figure 20.8 and figure 20.9) t mckh sck high time 1 x t sysclk ? ns t mckl sck low time 1 x t sysclk ? ns t mis miso valid to sck shift edge 1 x t sysclk + 20 ? ns t mih sck shift edge to miso change 0 ? ns slave mode timing* (se e figure 20.10 and figure 20.11) t se nss falling to first sck edge 2 x t sysclk ? ns t sd last sck edge to nss rising 2 x t sysclk ? ns t sez nss falling to miso valid ? 4 x t sysclk ns t sdz nss rising to miso high-z ? 4 x t sysclk ns t ckh sck high time 5 x t sysclk ? ns t ckl sck low time 5 x t sysclk ? ns t sis mosi valid to sck sample edge 2 x t sysclk ? ns t sih sck sample edge to mosi change 2 x t sysclk ? ns t soh sck shift edge to miso change ? 4 x t sysclk ns t slh last sck edge to miso change (ckpha = 1 only) 6 x t sysclk 8 x t sysclk ns *note: t sysclk is equal to one period of the device system clock (sysclk). c8051f360/1/2/3/4/5/6/7/8/9 246 rev. 1.0 rev. 1.0 247 c8051f360/1/2/3/4/5/6/7/8/9 21. timers each mcu includes four counter/timers: two are 16-bit counter/timers compatible with those found in the standard 8051, and two are 16-bit auto-reload timer fo r use with the adc, smbus, or for general purpose use. these timers can be used to measure time inte rvals, count external even ts and generate periodic interrupt requests. timer 0 and timer 1 are nearly identical and have four primary modes of operation. ti mer 2 and timer 3 offer 16-bit and split 8-bit timer functionality with auto-reload. timers 0 and 1 may be clocked by one of five sources, determined by the timer mode select bits (t1m ? t0m) and the clock scale bits (sca1 ? sca0). the clock scale bits define a pre-scaled clock from which timer 0 and/or timer 1 may be clocked (see sfr definition 21.3 for pre-scaled cl ock s election). timer 0/1 may then be configured to use this pre-sc ale d clock signal or th e system clock. timer 2 and t imer 3 may be clocked by the system clock, the system clock divided by 12, or the external oscillator clock source divided by 8. timer 0 and timer 1 may also be operated as counters. when fun ctioning as a counter, a counter/timer register is incremented on each high-to-low transition at the selected input pin (t0 or t1). events with a fre - quency of up to one-fourth the system clock frequen cy can be counted. the input signal need not be peri - odic, but it should be held at a gi ve n level for at least two full system cl ock cycles to ensure the level is properly sampled. timer 0 and timer 1 modes: ti mer 2 modes: timer 3 modes: 13-bit counter/timer 16-bit timer with auto-reload 16-bit timer with auto-reload 16-bit counter/timer 8-bit counter/timer with auto- reload two 8-bit timers with auto-reload t wo 8-bit timers with auto-reload two 8-bit counter/timers (timer 0 only) c8051f360/1/2/3/4/5/6/7/8/9 248 rev. 1.0 21.1. timer 0 and timer 1 each timer is implemented as a 16-bit register acce ssed as two separate bytes: a low byte (tl0 or tl1) and a high byte (th0 or th1). the counter/timer co ntrol register (tcon) is used to enable timer 0 and ti mer 1 as well as indicate status. timer 0 interrupts can be enabled by setting the et0 bit in the ie regis - ter ( section ?10.4. interrupt register descriptions? on page 109 ); timer 1 interrupts can be enabled by set - ting the et1 bit in the ie register ( section 10.4 ). both counter/timers operate in one of four primary modes selected by setting the mode select bits t1m1 ? t 0m0 in the counter/timer mode register (tmod). each timer can be configured independently. each operating mode is described below. 21.1.1. mode 0: 13-bit counter/timer timer 0 and timer 1 operate as 13-bit counter/timers in mode 0. the following describes the configuration a nd operation of timer 0. however, both timers operate identically, and timer 1 is configured in the same ma nner as described for timer 0. the th0 register holds the eight msbs of the 13-bit c oun ter/timer. tl0 holds the five lsbs in bit positions tl0.4 ? tl0.0. the three upper bits of tl0 (tl0.7 ? tl0.5) are indeterminate and should be masked out or ignored when reading. as the 13-bit timer register increments and overflows from 0x1fff (all ones) to 0x0000, the timer overflow flag tf0 (tcon.5) is set and an interr upt will occur if timer 0 interrupts are e nabled. the c/t0 bit (tmod.2) selects the counter/timer 's clock source. when c/t0 is set to logic ?1?, high-to-low tra nsitions at the selected timer 0 input pin (t0) increment the timer register (refer to section ?17.1. priority crossbar decoder? on page 185 for information on selecting and configuring external i/o pins). clearing c/t selects the clock defined by the t0m bit (ckcon.3). when t0m is set, timer 0 is clocked by the system clock. when t0m is cleared, timer 0 is clocked by the source selected by the clock scale bits in ckcon (see sfr definition 21.3 ). setting the tr0 bit (tcon.4) enables the ti me r when either gate0 (tmod.3) is logic ?0? or the input signal /in t0 is active as defined by bit in0pl in register it01cf (see sfr definition 10.7 ). setting gate0 to ?1? allows the timer to be controlled by th e external input signal /int0 (see section ?10.4. interrupt register descriptions? on page 109 ), facilitating pulse width measurements note: x = don't care setting tr0 does not force the timer to reset. the timer registers should be loaded with the desired initial value before the timer is enabled. tl1 and th1 form the 13-bit register for timer 1 in the same manner as described above for tl0 and th0. ti mer 1 is configured and controlled using the releva nt tcon and tmod bits just as with timer 0. the in put signal /int1 is used with timer 1; the /int1 polarity is defined by bit in1pl in register it01cf (see sfr definition 10.7 ). tr0 gate0 /int0 counter/timer 0 x x disabled 1 0 x enabled 1 1 0 disabled 111 e n a b l e d tclk tl0 (5 bits) th0 (8 bits) tcon tf0 tr0 tr1 tf1 ie 1 it1 ie 0 it0 interrupt tr0 0 1 0 1 sysclk pre-scaled clock ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m tmod t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 gate0 /int0 t0 crossbar it01cf i n 1 s l 1 i n 1 s l 0 i n 1 s l 2 i n 1 p l i n 0 p l i n 0 s l 2 i n 0 s l 1 i n 0 s l 0 in 0pl xor rev. 1.0 249 c8051f360/1/2/3/4/5/6/7/8/9 figure 21.1. t0 mode 0 block diagram 21.1.2. mode 1: 16-bit counter/timer mode 1 operation is the same as mode 0, except that the counte r /timer registers use all 16 bits. the cou nter/timers are enabled and configured in mode 1 in the same manner as for mode 0. 21.1.3. mode 2: 8-bit counter/timer with auto-reload mode 2 configures timer 0 and timer 1 to operate as 8-bit counter/timers with automatic reload of the start valu e. tl0 holds the count and th0 holds the reload va lue. when the counter in tl0 overflows from all ones to 0x00, the timer over flow flag tf0 (tcon.5) is set and the counter in tl0 is reloaded from th0. if timer 0 interrupts are enabled, an interr upt will occ ur when the tf0 flag is set. the reload value in th0 is not changed. tl0 must be initialized to the desired va lue before enabling the timer for the first count to be correct. when in mode 2, timer 1 operates identically to timer 0. both counter/timers are enabled and configured in mode 2 in the same manner as mode 0. setting the tr0 bit (tcon.4) enables the timer when either gate0 (tmod.3) is logic ?0? or when the input signal /int 0 is active as defined by bit in0pl in register it01cf (see section ?10.5. external interrupts? on page 115 for details on the external input signals /int0 and /int1). tclk tmod t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 tcon tf0 tr0 tr1 tf1 ie1 it1 ie0 it0 interrupt tl0 (8 bits) reload th0 (8 bits) 0 1 0 1 sysclk pre-scaled clock it01cf i n 1 s l 1 i n 1 s l 0 i n 1 s l 2 i n 1 p l i n 0 p l i n 0 s l 2 i n 0 s l 1 i n 0 s l 0 tr0 gate0 in0pl xor /int0 t0 crossbar ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m c8051f360/1/2/3/4/5/6/7/8/9 250 rev. 1.0 figure 21.2. t0 mode 2 block diagram rev. 1.0 251 c8051f360/1/2/3/4/5/6/7/8/9 21.1.4. mode 3: two 8-bit counter/timers (timer 0 only) in mode 3, timer 0 is configured as two separate 8-bit co un ter/timers held in tl0 and th0. the counter/timer in tl0 is controlled using the timer 0 control/status bits in tcon and tmod: tr0, c/t0, ga te0 and tf0. tl0 can use either the system clock or an external input signal as its timebase. the th0 register is restricted to a timer function sourced by the system clock or prescaled clock. th0 is enabled using the timer 1 run control bit tr1. th0 sets the timer 1 overflow flag tf1 on overflow and thus controls the t imer 1 interrupt. timer 1 is inactive in mode 3. when timer 0 is operating in mode 3, timer 1 can be operated in modes 0, 1 or 2, but cannot be clocked by external signals nor set the tf1 flag and generate an interrupt. however, the timer 1 overflow can be used to generate baud rates for the smbus and/or uart, and/or initiate adc conv ersions. while timer 0 is operating in mode 3, timer 1 run control is handled through its mode set - tings. to run timer 1 while timer 0 is in mode 3, set the timer 1 mode as 0, 1, or 2. to disable timer 1, con figure it for mode 3. tl0 (8 bits) tmod 0 1 tcon tf0 tr0 tr1 tf1 ie1 it1 ie0 it0 interrupt interrupt 0 1 sysclk pre-scaled clock tr1 th0 (8 bits) t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 tr0 gate0 in0pl xor /int0 t0 crossbar ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m figure 21.3. t0 mode 3 block diagram c8051f360/1/2/3/4/5/6/7/8/9 252 rev. 1.0 sfr definition 21.1. tcon: timer control bit 7: tf1: timer 1 overflow flag. set by hardware when timer 1 overflows. this flag can be cleared by software but is auto- matically cleared when the cpu vectors to the timer 1 interrupt service routine. 0: no timer 1 overflow detected. 1: timer 1 has overflowed. bit 6: tr1: timer 1 run control. 0: timer 1 disabled. 1: timer 1 enabled. bit 5: tf0: timer 0 overflow flag. set by hardware when timer 0 overflows. this flag can be cleared by software but is auto- matically cleared when the cpu vectors to the timer 0 interrupt service routine. 0: no timer 0 overflow detected. 1: timer 0 has overflowed. bit 4: tr0: timer 0 run control. 0: timer 0 disabled. 1: timer 0 enabled. bit 3: ie1: external interrupt 1. this flag is set by hardware when an edge/level of type defined by it1 is detected. it can be cleared by software but is automatically cl eared when the cpu vectors to the external interrupt 1 service routine if it1 = 1. when it1 = 0, this flag is set to ?1? when /int1 is active as defined by bit in1pl in register it01cf (see sfr definition 10.7). bit 2: it1: interrupt 1 type select. this bit selects whether the co nfigured /int1 interrupt will be edge or level sensitive. /int1 is configured active low or high by the in1pl bit in the it01cf register (see sfr definition 10.7). 0: /int1 is level triggered. 1: /int1 is edge triggered. bit 1: ie0: external interrupt 0. this flag is set by hardware when an edge/level of type defined by it0 is detected. it can be cleared by software but is automatically cl eared when the cpu vectors to the external interrupt 0 service routine if it0 = 1. when it0 = 0, this flag is set to ?1? when /int0 is active as defined by bit in0pl in register it01cf (see sfr definition 10.7). bit 0: it0: interrupt 0 type select. this bit selects whether the co nfigured /int0 interrupt will be edge or level sensitive. /int0 is configured active low or high by the in0p l bit in register it01cf (see sfr definition 10.7). 0: /int0 is level triggered. 1: /int0 is edge triggered. sfr page: sfr address: all pages 0x88 (bit addressable) r/w r/w r/w r/w r/w r/w r/w r/w reset value tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rev. 1.0 253 c8051f360/1/2/3/4/5/6/7/8/9 sfr definition 21.2. tmod: timer mode bit 7: gate1: timer 1 gate control. 0: timer 1 enabled when tr1 = 1 irrespective of /int1 logic level. 1: timer 1 enabled only when tr1 = 1 and /int1 is active as defined by bit in1pl in regis- ter it01cf (see sfr definition 10.7). bit 6: c/t1: counter/timer 1 select. 0: timer function: timer 1 incremented by clock defined by t1m bit (ckcon.4). 1: counter function: timer 1 incremented by high-to-low transitions on external input pin (t1). bits 5 ? 4: t1m1 ? t1m0: timer 1 mode select. these bits select the timer 1 operation mode. bit 3: gate0: timer 0 gate control. 0: timer 0 enabled when tr0 = 1 irrespective of /int0 logic level. 1: timer 0 enabled only when tr0 = 1 and /int0 is active as defined by bit in0pl in regis- ter it01cf (see sfr definition 10.7). bit 2: c/t0: counter/timer select. 0: timer function: timer 0 incremented by clock defined by t0m bit (ckcon.3). 1: counter function: timer 0 incremented by high-to-low transitions on external input pin (t0). bits 1 ? 0: t0m1 ? t0m0: timer 0 mode select. these bits select the timer 0 operation mode. sfr page: sfr address: all pages 0x89 r/w r/w r/w r/w r/w r/w r/w r/w reset value gate1 c/t1 t1m1 t1m0 gate0 c/t0 t0m1 t0m0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 t1m1 t1m0 mode 0 0 mode 0: 13-bit counter/timer 0 1 mode 1: 16-bit counter/timer 1 0 mode 2: 8-bit counter/timer with auto-reload 1 1 mode 3: timer 1 inactive t0m1 t0m0 mode 0 0 mode 0: 13-bit counter/timer 0 1 mode 1: 16-bit counter/timer 1 0 mode 2: 8-bit counter/timer with auto-reload 1 1 mode 3: two 8-bit counter/timers c8051f360/1/2/3/4/5/6/7/8/9 254 rev. 1.0 sfr definition 21.3. ckcon: clock control bit 7: t3mh: timer 3 high byte clock select. this bit selects the clock supplied to the timer 3 high byte if timer 3 is configured in split 8- bit timer mode. t3mh is ignored if time 3 is in any other mode. 0: timer 3 high byte uses the clock defined by the t3xclk bit in tmr3cn. 1: timer 3 high byte uses the system clock. bit 6: t3ml: timer 3 low byte clock select. this bit selects the clock supplie d to timer 3. if timer 3 is c onfigured in split 8-bit timer mode, this bit selects the clock supplied to the lower 8-bit timer. 0: timer 3 low byte uses the clock defined by the t3xclk bit in tmr3cn. 1: timer 3 low byte uses the system clock. bit 5: t2mh: timer 2 high byte clock select. this bit selects the clock supplied to the timer 2 high byte if timer 2 is configured in split 8- bit timer mode. t2mh is ignored if timer 2 is in any other mode. 0: timer 2 high byte uses the clock defined by the t2xclk bit in tmr2cn. 1: timer 2 high byte uses the system clock. bit 4: t2ml: timer 2 low byte clock select. this bit selects the clock supplie d to timer 2. if timer 2 is c onfigured in split 8-bit timer mode, this bit selects the clock supplied to the lower 8-bit timer. 0: timer 2 low byte uses the clock defined by the t2xclk bit in tmr2cn. 1: timer 2 low byte uses the system clock. bit 3: t1m: timer 1 clock select. this select the clock source supplied to timer 1. t1m is ig nored when c/t1 is set to logic ?1?. 0: timer 1 uses the clock defined by the prescale bits, sca1 ? sca0. 1: timer 1 uses the system clock. bit 2: t0m: timer 0 clock select. this bit selects the clock source supplied to timer 0. t0m is ignored when c/t0 is set to logic ?1?. 0: counter/timer 0 uses the clock defined by the prescale bits, sca1 ? sca0. 1: counter/timer 0 uses the system clock. bits 1 ? 0: sca1 ? sca0: timer 0/1 prescale bits. these bits control the division of the clock su pplied to timer 0 and/or timer 1 if configured to use prescaled clock inputs. sfr page: sfr address: all pages 0x8e r/w r/w r/w r/w r/w r/w r/w r/w reset value t3mh t3ml t2mh t2ml t1m t0m sca1 sca0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sca1 sca0 prescaled clock 0 0 system clock divided by 12 0 1 system clock divided by 4 1 0 system clock divided by 48 1 1 external clock divided by 8 note: external clock divided by 8 is synchronized with the system clock. rev. 1.0 255 c8051f360/1/2/3/4/5/6/7/8/9 sfr definition 21.4. tl0: timer 0 low byte bits 7 ? 0: tl0: timer 0 low byte. the tl0 register is the low byte of the 16-bit timer 0. sfr page: sfr address: all pages 0x8a r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr definition 21.5. tl1: timer 1 low byte bits 7 ? 0: tl1: timer 1 low byte. the tl1 register is the low byte of the 16-bit timer 1. sfr page: sfr address: all pages 0x8b r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr definition 21.6. th0: timer 0 high byte bits 7 ? 0: th0: timer 0 high byte. the th0 register is the high byte of the 16-bit timer 0. sfr page: sfr address: all pages 0x8c r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr definition 21.7. th1: timer 1 high byte bits 7 ? 0: th1: timer 1 high byte. the th1 register is the high byte of the 16-bit timer 1. sfr page: sfr address: all pages 0x8d r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: c8051f360/1/2/3/4/5/6/7/8/9 256 rev. 1.0 21.2. timer 2 timer 2 is a 16-bit timer formed by two 8-bit sfrs: tmr2l (low byte) and tmr2h (high byte). timer 2 may o perate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. the t2split bit (tmr2cn.3) defines the timer 2 operation mode. timer 2 may be clocked by the system c lock, the system clock divided by 12, or the external oscillator source divided by 8. the external clock mode is ideal for real-time clock (rtc) functionality, where the internal oscillator drives t he system clock while timer 2 (and/or the pca) is clocked by an external preci - sion oscillator. note that the external oscillator source divided by 8 is synchronized with the system clock. 21.2.1. 16-bit timer with auto-reload when t2split (tmr2cn. 3) is zero, timer 2 operates as a 16-bit time r with auto-reload. timer 2 can be clocked by s ysclk, sysclk divided by 12, or the exte rnal oscillator clock source divided by 8. as the 16-bit timer register increments and overflows from 0xffff to 0x0000, the 16-bit value in the timer 2 reload registers (tmr2rlh and tmr2rll) is loaded into the timer 2 register as shown in figure 21.4 , and the timer 2 high byte overflow flag (tmr2cn.7) is set. if timer 2 interrupts are enabled (if ie.5 is set), an interrupt will be gen erated on each timer 2 overflow. additionally, if timer 2 interrupts are enabled and the tf2len bit is set (tmr2cn. 5), an interr upt will be generated each time the lower 8 bits (tmr2l) overflow from 0xff to 0x00. external clock / 8 sysclk / 12 sysclk tmr2l tmr2h tmr2rll tmr2rlh reload tclk 0 1 tr2 tmr2cn t2split tf2cen tf2l tf2h t2xclk tr2 0 1 t2xclk interrupt tf2len to adc, smbus to smbus tl2 overflow ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m figure 21.4. timer 2 16-bi t mode block diagram rev. 1.0 257 c8051f360/1/2/3/4/5/6/7/8/9 21.2.2. 8-bit timers with auto-reload when t2split is set, timer 2 operates as two 8-bit timers (tmr2h an d tmr2l). both 8-bit timers oper - ate in auto-reload mode as shown in figure 21.5 . tmr2rll holds the reload va lue for tmr2l; tmr2rlh holds the reload value for tmr2h. the tr 2 bit in tmr2cn handles the run control for tmr2h. tmr2l is always running when configured for 8-bit mode. each 8-bit timer may be c onfigured to use sys clk, sysclk divided by 12, or the external oscillator clock source divided by 8. the timer 2 clock select bits (t2mh and t2ml in ckcon) select either sysclk or the clock defined by the timer 2 external clock select bit (t 2xc lk in tmr2cn), as follows: the tf2h bit is set when tmr2h overflows from 0xff to 0x00 ; the tf2l bit is set when tmr2l overflows from 0xff to 0x00. when timer 2 interrupts are enabled (ie.5), an interrupt is generated each time tm r2h overflows. if timer 2 interrupts are enabled and tf2len (tmr2cn.5) is set, an interrupt is gener - ated each time either tmr2l or tmr2h overflows. wh en tf2len is enabled, software must check the tf2h and tf2l flags to determine the source of the timer 2 interrupt. the tf2h and tf2l interrupt flags a re not cleared by hardware and must be manually cleared by software. sysclk tclk 0 1 tr2 external clock / 8 sysclk / 12 0 1 t2xclk 1 0 tmr2h tmr2rlh reload reload tclk tmr2l tmr2rll interrupt tmr2cn t2split tf2cen tf2len tf2l tf2h t2xclk tr2 to adc, smbus to smbus ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m figure 21.5. timer 2 8- bit mode block diagram t2mh t2xclk tmr2h clock source t2ml t2xclk tmr2l clock source 0 0 sysclk/12 0 0 sysclk/12 0 1 external clock/8 0 1 external clock/8 1 x sysclk 1 x sysclk c8051f360/1/2/3/4/5/6/7/8/9 258 rev. 1.0 sfr definition 21.8. tmr2cn: timer 2 control bit 7: tf2h: timer 2 high byte overflow flag. set by hardware when the timer 2 high byte ov erflows from 0xff to 0x00. in 16 bit mode, this will occur when timer 2 overflows from 0x ffff to 0x0000. when the timer 2 interrupt is enabled, setting this bit causes the cpu to vector to the timer 2 interrupt service routine. tf2h is not automatically cleared by hard ware and must be cleared by software. bit 6: tf2l: timer 2 low byte overflow flag. set by hardware when the timer 2 low byte over flows from 0xff to 0x00. when this bit is set, an interrupt will be generat ed if tf2len is set and timer 2 interrupts are enabled. tf2l will set when the low byte overflows regardless of the timer 2 mode. this bit is not automat- ically cleared by hardware. bit 5: tf2len: timer 2 low byte interrupt enable. this bit enables/disables timer 2 low byte in terrupts. if tf2len is set and timer 2 inter- rupts are enabled, an interrupt will be generated when the low byte of timer 2 overflows. 0: timer 2 low byte interrupts disabled. 1: timer 2 low byte interrupts enabled. bit 4: tf2cen: timer 2 low-frequency oscilla tor capture enable. this bit enables/disables timer 2 low-frequency oscillator capture mode. if tf2cen is set and timer 2 interrupts are enabled, an in terrupt will be generated on a falling edge of the low-frequency oscillator output, and the current 16 -bit timer value in tmr2h:tmr2l will be copied to tmr2rlh:tmr2rll. se e section ?16. oscillators? on page 169 for more details. 0: timer 2 low-frequency oscillator capture disabled. 1: timer 2 low-frequency oscillator capture enabled. bit 3: t2split: timer 2 split mode enable. when this bit is set, timer 2 operates as two 8-bit timers with auto-reload. 0: timer 2 operates in 16-bit auto-reload mode. 1: timer 2 operates as two 8-bit auto-reload timers. bit 2: tr2: timer 2 run control. this bit enables/disables timer 2. in 8-bit mode, this bit enables/disables tmr2h only; tmr2l is always enabled in this mode. 0: timer 2 disabled. 1: timer 2 enabled. bit 1: unused. read = 0b. write = don?t care. bit 0: t2xclk: timer 2 external clock select. this bit selects the external cl ock source for timer 2. if timer 2 is in 8-bit mode, this bit selects the external o scillator clock source fo r both timer bytes. however, the timer 2 clock select bits (t2mh and t2ml in register ck con) may still be used to select between the external clock and the system clock for either timer. 0: timer 2 external clock selection is the system clock divided by 12. 1: timer 2 external clock selection is the external clock divided by 8. note that the external oscillator source divided by 8 is synchronized with the system clock. sfr page: sfr address: all pages 0xc8 (bit addressable) r/w r/w r/w r/w r/w r/w r r/w reset value tf2h tf2l tf2len tf2cen t2split tr2 ? t2xclk 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rev. 1.0 259 c8051f360/1/2/3/4/5/6/7/8/9 sfr definition 21.9. tmr2rll: timer 2 relo ad register low byte bits 7 ? 0: tmr2rll: timer 2 reload register low byte. tmr2rll holds the low byte of the reload value for timer 2. sfr page: sfr address: all pages 0xca r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr definition 21.10. tmr2rlh: timer 2 relo ad register high byte bits 7 ? 0: tmr2rlh: timer 2 reload register high byte. the tmr2rlh holds the high byte of the reload value for timer 2. sfr page: sfr address: all pages 0xcb r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr definition 21.11. tmr2l: timer 2 low byte bits 7 ? 0: tmr2l: timer 2 low byte. in 16-bit mode, the tmr2l register contains the low byte of the 16-bit timer 2. in 8-bit mode, tmr2l contains the 8-bit low byte timer value. sfr page: sfr address: all pages 0xcc r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr definition 21.12. tmr2h timer 2 high byte bits 7 ? 0: tmr2h: timer 2 high byte. in 16-bit mode, the tmr2h register contains t he high byte of the 16-bit timer 2. in 8-bit mode, tmr2h contains the 8-bit high byte timer value. sfr page: sfr address: all pages 0xcd r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 c8051f360/1/2/3/4/5/6/7/8/9 260 rev. 1.0 21.3. timer 3 timer 3 is a 16-bit timer formed by two 8-bit sfrs: tmr3l (low byte) and tmr3h (high byte). timer 3 may operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. the t3split bit (tmr3cn.3) defines the timer 3 operation mode. timer 3 may be clocked by the system clock, the sy stem clock divided by 12, or the external oscillator source divided by 8. the external clock mode is ideal for real-time clock (rtc) functionality, where the internal oscillator drives t he system clock while timer 3 (and/or the pca) is clocked by an external preci - sion oscillator. note that the external oscillator source divided by 8 is synchronized with the system clock. 21.3.1. 16-bit timer with auto-reload when t3split (tmr3cn.3) is zero, timer 3 operates as a 16-bit timer with auto-reload. timer 3 can be clocked by sysclk, sysclk divided by 12, or the exte rnal oscillator clock source divided by 8. as the 16-bit timer register increments and overflows from 0xffff to 0x0000, the 16-bit value in the timer 3 reload registers (tmr3rlh and tmr3rll) is load ed into the timer 3 register as shown in figure 21.6 , and the timer 3 high byte overflow flag (t mr3cn.7) is set. if timer 3 interrupts are enabled (if eie1.7 is set), an interrupt will be generat ed on each timer 3 overflow. additiona lly, if timer 3 inte rrupts are enabled and the tf3len bit is set (tmr3cn. 5), an interr upt will be generated each time the lower 8 bits (tmr3l) overflow from 0xff to 0x00. external clock / 8 sysclk / 12 sysclk tmr3l tmr3h tmr3rll tmr3rlh reload tclk 0 1 tr3 tmr3cn t3split tf3cen tf3l tf3h t3xclk tr3 0 1 t3xclk interrupt tf3len to adc ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m figure 21.6. timer 3 16-bi t mode block diagram rev. 1.0 261 c8051f360/1/2/3/4/5/6/7/8/9 21.3.2. 8-bit timers with auto-reload when t3split is set, timer 3 operates as two 8-bi t timers (tmr3h and tmr3l). both 8-bit timers oper - ate in auto-reload mode as shown in figure 21.7 . tmr3rll holds the reload va lue for tmr3l; tmr3rlh holds the reload value for tmr3h. the tr 3 bit in tmr3cn handles the run control for tmr3h. tmr3l is always running when configured for 8-bit mode. each 8-bit timer may be c onfigured to use sys clk, sysclk divided by 12, or the external oscillator clock source divided by 8. the timer 3 clock select bits (t3mh and t3ml in ckcon) select either sysclk or the clock defined by the timer 3 external cloc k select bit (t3xclk in tmr3cn), as follows: the tf3h bit is set when tmr3h overflows from 0xff to 0x00 ; the tf3l bit is set when tmr3l overflows from 0xff to 0x00. when timer 3 interrupts are enabled, an interrupt is generated each time tmr3h over - flows. if timer 3 interrupts are enabled and tf3len (tm r3cn.5) is set, an interrupt is generated each time either tmr3l or tmr3h overflows. when tf3le n is enabled, software must check the tf3h and tf3l flags to determine the source of the timer 3 interrupt. the tf3h and tf3l interrupt flags are not cleared by hardware and must be manually cleared by software. sysclk tclk 0 1 tr3 external clock / 8 sysclk / 12 0 1 t3xclk 1 0 tmr3h tmr3rlh reload reload tclk tmr3l tmr3rll interrupt tmr3cn t3split tf3cen tf3len tf3l tf3h t3xclk tr3 to adc ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m figure 21.7. timer 3 8- bit mode block diagram t3mh t3xclk tmr3h clock source t3ml t3xclk tmr3l clock source 0 0 sysclk/12 0 0 sysclk/12 0 1 external clock/8 0 1 external clock/8 1 x sysclk 1 x sysclk c8051f360/1/2/3/4/5/6/7/8/9 262 rev. 1.0 sfr definition 21.13. tmr3cn: timer 3 control bit 7: tf3h: timer 3 high byte overflow flag. set by hardware when the timer 3 high byte ov erflows from 0xff to 0x00. in 16 bit mode, this will occur when timer 3 overflows from 0xff ff to 0x0000. when the timer 3 inte rrupt is enabled, setting this bit causes the cpu to vector to the timer 3 interrupt service routine. tf3h is not automatically cleared by hard ware and must be cleared by software. bit 6: tf3l: timer 3 low byte overflow flag. set by hardware when the timer 3 low byte over flows from 0xff to 0x00. when this bit is set, an interrupt will be generated if tf3len is set and timer 3 interr upts are enabled. tf3l will set when the low byte overflows regardless of the timer 3 mode. this bit is not automat- ically cleared by hardware. bit 5: tf3len: timer 3 low byte interrupt enable. this bit enables/disables timer 3 low byte in terrupts. if tf3len is set and timer 3 inter- rupts are enabled, an interrupt will be generated when the low byte of timer 3 overflows. 0: timer 3 low byte interrupts disabled. 1: timer 3 low byte interrupts enabled. bit 4: tf3cen: timer 3 low-frequency oscilla tor capture enable. this bit enables/disables timer 3 low-frequency oscillator capture mode. if tf3cen is set and timer 3 interrupts are enabled, an in terrupt will be generated on a rising edge of the low-frequency oscillator output, and the current 16 -bit timer value in tmr3h:tmr3l will be copied to tmr3rlh:tmr3rll. se e section ?16. oscillators? on page 169 for more details. 0: timer 3 low-frequency oscillator capture disabled. 1: timer 3 low-frequency oscillator capture enabled. bit 3: t3split: timer 3 split mode enable. when this bit is set, timer 3 operates as two 8-bit timers with auto-reload. 0: timer 3 operates in 16-bit auto-reload mode. 1: timer 3 operates as two 8-bit auto-reload timers. bit 2: tr3: timer 3 run control. this bit enables/disables timer 3. in 8-bit mode, this bit enables/disables tmr3h only; tmr3l is always enabled in this mode. 0: timer 3 disabled. 1: timer 3 enabled. bit 1: unused. read = 0b. write = don?t care. bit 0: t3xclk: timer 3 external clock select. this bit selects the external cl ock source for timer 3. if timer 3 is in 8-bit mode, this bit selects the external o scillator clock source for both time r bytes. however, the timer 3 clock select bits (t3mh and t3ml in register ck con) may still be used to select between the external clock and the system clock for either timer. 0: timer 3 external clock selection is the system clock divided by 12. 1: timer 3 external clock selection is the external clock divided by 8. note that the external oscillator source divided by 8 is synchronized with the system clock. sfr page: sfr address: all pages 0x91 r/w r/w r/w r/w r/w r/w r r/w reset value tf3h tf3l tf3len tf3cen t3split tr3 ? t3xclk 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rev. 1.0 263 c8051f360/1/2/3/4/5/6/7/8/9 sfr definition 21.14. tmr3rll: timer 3 reload register low byte bits 7 ? 0: tmr3rll: timer 3 reload register low byte. tmr3rll holds the low byte of the reload value for timer 3. sfr page: sfr address: all pages 0x92 r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr definition 21.15. tmr3rlh: timer 3 relo ad register high byte bits 7 ? 0: tmr3rlh: timer 3 reload register high byte. the tmr3rlh holds the high byte of the reload value for timer 3. sfr page: sfr address: all pages 0x93 r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr definition 21.16. tmr3l: timer 3 low byte bits 7 ? 0: tmr3l: timer 3 low byte. in 16-bit mode, the tmr3l register contains the low byte of the 16-bit timer 3. in 8-bit mode, tmr3l contains the 8-bit low byte timer value. sfr page: sfr address: all pages 0x94 r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr definition 21.17. tmr3h timer 3 high byte bits 7 ? 0: tmr3h: timer 3 high byte. in 16-bit mode, the tmr3h register contains t he high byte of the 16-bit timer 3. in 8-bit mode, tmr3h contains the 8-bit high byte timer value. sfr page: sfr address: all pages 0x95 r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 c8051f360/1/2/3/4/5/6/7/8/9 264 rev. 1.0 22. programmable counter array the programmable counter array (pca0) provides enhanced timer functionality while requiring less cpu intervention than the standard 8051 counter/timers. pc a0 consists of a dedicated 16-bit counter/timer and six 16-bit capture/compare modules. each capture/compare module has its own associated i/o line (cexn) which is routed through the crossbar to port i/o when enabled (see section ?17.3. general pur - pose port i/o? on page 190 ). the counter/timer is driven by a pr ogrammable timebase that can select between six inputs as its source: system clock, system clock divided by four, system clock divided by twelve, the external oscillator clock so urce divided by 8, timer 0 overflow, or an external clock signal on the eci line. each capture/compare module may be confi gured to operate independently in one of six modes: edge-triggered capture, software timer, high-speed output, frequency output, 8-bit pwm, or 16-bit pwm (each is described in section 22.2 ). the pca is confi gured and controlled t h rough the system con - troller's special function registers. th e basic pca block diagram is shown in figure 22.1 . important note: t he pca module 5 may be used as a watchdog timer (wdt), and is enabled in this mode following a system reset. access to certain pca registers is restricted while wdt mode is enabled . see section 22.3 for details. capture/compare module 1 capture/compare module 0 capture/compare module 2 capture/compare module 3 cex1 eci crossbar cex2 cex3 cex0 port i/o 16-bit counter/timer pca clock mux sysclk/12 sysclk/4 timer 0 overflow eci sysclk external clock/8 capture/compare module 4 cex4 capture/compare module 5 cex5 figure 22.1. pca block diagram rev. 1.0 265 c8051f360/1/2/3/4/5/6/7/8/9 22.1. pca counter/timer the 16-bit pca counter/timer consists of two 8-bi t sfrs: pca0l and pca0h. pca0h is the high byte (msb) of the 16-bit counter/timer and pca0l is the lo w byte (lsb). reading pc a0l automatically latches the value of pca0h into a ?snapshot? register; the following pca0h read accesses this ?snapshot? register. reading the pca0l register first guarantees an accu rate reading of the entire 16-bit pca0 counter. read - ing pca0h or pca0l does not disturb the counter op e ration. the cps2?cps0 bits in the pca0md regis - ter select the timebase for the counter/timer as shown in ta b l e 22.1 . when the counter/timer overflows from 0xffff to 0x0 000 , the counter overflow fl ag (cf) in pca0md is set to logic ?1? and an interrupt request is generated if cf interrupts are enabled. setting the ecf bit in pca0md to logic ?1? enables the cf flag to generate an interrupt request. the cf bit is not automatically cleared by hardware when the cpu vectors to the in terrupt service routine, and must be cleared by soft - ware (note: pca0 interrupts must be globally enabled before cf interrupts are recognized. pca0 inter - rupts are globally enabled by setting the ea bit (ie.7) and the epca0 bit in eie1 to logic ?1?). clearing the cidl bit in the pca0md register a llows the pca to continue normal op eration while the cpu is in idle mode. table 22.1. pca timebase input options *note: external clock divided by 8 is synchronized with the system clock. pca0md c i d l w d t e e c f c p s 1 c p s 0 w d l c k c p s 2 idle 0 1 pca0h pca0l snapshot register to sfr bus overflow to pca interrupt system cf pca0l read to pca modules sysclk/12 sysclk/4 timer 0 overflow eci 000 001 010 011 100 101 sysclk external clock/8 pca0cn c f c r c c f 0 c c f 2 c c f 1 c c f 5 c c f 4 c c f 3 figure 22.2. pca counter /timer block diagram cps2 cps1 cps0 timebase 0 0 0 system clock divided by 12 0 0 1 system clock divided by 4 0 1 0 timer 0 overflow 0 1 1 high-to-low transitions on eci (max rate = system clock divided by 4) 1 0 0 system clock 1 0 1 external oscillator source divided by 8* 110reserved 111reserved c8051f360/1/2/3/4/5/6/7/8/9 266 rev. 1.0 22.2. capture/compare modules each module can be configured to operate independently in one of six operation modes: edge-triggered capture, software timer, high speed output, frequency output, 8-bit pulse width modulator, or 16-bit pulse width modulator. each module has special func tion registers (sfrs) asso ciated with it in the cip- 51 system controller. these registers are used to exchange data with a module and configure the module's mode of operation. ta b l e 22.2 summarizes the bit settings in the pca0cpmn r egisters used to select the pca0 capture/com - pare module?s operating modes. setting the eccfn bi t in a pca0cpmn register enables the module's ccfn interrupt. note: pca0 interrupts must be globally enabled before individual ccfn interrupts are rec - ognized. pca0 interrupts are globally enabled by sett in g the ea bit (ie.7) and the epca0 bit (eie1.3) to logic ?1?. see figure 22.3 for details on the pca interrupt configuration. pca0cn c f c r c c f 0 c c f 2 c c f 1 c c f 5 c c f 4 c c f 3 pca0md c i d l e c f c p s 1 c p s 0 c p s 2 0 1 pca module 0 (ccf0) pca module 1 (ccf1) eccf1 0 1 eccf0 0 1 pca module 2 (ccf2) eccf2 0 1 pca module 3 (ccf3) eccf3 eccf4 pca counter/ timer overflow 0 1 interrupt priority decoder epca0 (eie.3) pca0cpmn (for n = 0 to 5) p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n 0 1 pca module 4 (ccf4) 0 1 pca module 5 (ccf5) 0 1 ea (ie.7) 0 1 eccf5 figure 22.3. pca interrupt block diagram table 22.2. pca0cpm register settings for p ca capture/compare modules rev. 1.0 267 c8051f360/1/2/3/4/5/6/7/8/9 22.2.1. edge-triggered capture mode in this mode, a valid transition on the cexn pin caus es pca0 to capture the value of the pca0 counter/ timer and load it into the corresponding module's 16-bit capture/compare register (pca0cpln and pca0cphn). the cappn and capnn bits in the pca0cpmn register are used to select the type of transi - tion that triggers the capture: low-to-high transition (p o sitive edge), high-to-low transition (negative edge), or either transition (positive or negative edge). when a capture occurs, the capture/compare flag (ccfn) in pca0cn is set to logic ?1? and an interrupt request is generated if ccf interrupts are enabled. the ccfn bit is not automatically cleared by hardware when the cpu vectors to the interrupt service routine, and must be cleared by soft ware. if both cappn and c apnn bits are set to logic ?1?, then the state of the port pin associated w ith cexn can be read directly to determine wh ether a rising-edge or falling-edge caused the capture. pca0l pca0cpln pca timebase cexn crossbar port i/o pca0h capture pca0cphn 0 1 0 1 (to ccfn) pca interrupt pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n pca0cn c f c r c c f 0 c c f 2 c c f 1 c c f 5 c c f 4 c c f 3 figure 22.4. pca capture mode diagram note: the signal at cexn must be high or low for at least 2 system clock cycles to be recognized by the hardware. pwm16 ecom capp capn mat tog pwm eccf operation mode xx 10000x capture triggered by positive edge on cexn xx01000x capture triggered by negative edge on cexn xx11000x capture triggered by transition on cexn x 1 0 0 1 0 0 x software timer x 1 0 0 1 1 0 x high speed output x 1 0 0 0 1 1 x frequency output 0 1 0 0 0 0 1 0 8-bit pulse width modulator 1 1 0 0 0 0 1 0 16-bit pulse width modulator x = don?t care c8051f360/1/2/3/4/5/6/7/8/9 268 rev. 1.0 22.2.2. software timer (compare) mode in software timer mode, the pca0 counter/timer is co mpared to the module's 16-bit capture/compare reg - ister (pca0cphn and pca0cpln). when a match oc cu rs, the capture/compare flag (ccfn) in pca0cn is set to logic ?1? and an interrupt request is generated if ccf interrupts are enabled. the ccfn bit is not automatically cleared by hardware when the cpu vect ors to the interrupt service routine, and must be cleared by software. setting the ecomn and matn bits in the pca0cpmn register enables software timer mode. important note about capture/compare registers : wh en writing a 16-bit value to the pca0 capture/ compare registers, the low byte should always be wri tten first. writing to pca0cpln clears the ecomn bit to ?0?; writing to pca0 cphn sets ecomn to ?1?. match 16-bit comparator pca0h pca0cphn enable pca0l pca timebase pca0cpln 00 00 pca interrupt 0 1 x enb enb 0 1 write to pca0cpln write to pca0cphn reset pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n x pca0cn c f c r c c f 0 c c f 2 c c f 1 c c f 5 c c f 4 c c f 3 figure 22.5. pca software timer mode diagram rev. 1.0 269 c8051f360/1/2/3/4/5/6/7/8/9 22.2.3. high speed output mode in high speed output mode, a module?s associated cexn pin is toggled each time a match occurs between the pca counter and the module's 16- bit capture/compare register (pca0cphn and pca0cpln) setting the togn, matn, and ecomn bits in the pca0cpmn register enables the high- speed output mode. important note about capture/compare registers : wh en writing a 16-bit value to the pca0 capture/ compare registers, the low byte should always be wri tten first. writing to pca0cpln clears the ecomn bit to ?0?; writing to pca0 cphn sets ecomn to ?1?. match 16-bit comparator pca0h pca0cphn enable pca0l pca timebase pca0cpln pca interrupt 0 1 00 0x enb enb 0 1 write to pca0cpln write to pca0cphn reset pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n x cexn crossbar port i/o toggle 0 1 togn pca0cn c f c r c c f 0 c c f 2 c c f 1 c c f 5 c c f 4 c c f 3 figure 22.6. pca high speed output mode diagram note: the initial state of the to ggle output is logic ?1? and is initializ ed to this state when the module enters high speed output mode. c8051f360/1/2/3/4/5/6/7/8/9 270 rev. 1.0 22.2.4. frequency output mode frequency output mode produces a programmable-freq uency square wave on the module?s associated cexn pin. the capture/compare module high byte holds the number of pca clocks to count before the out - put is toggled. the frequency of the square wave is then defined by equation 22.1 . equation 22.1. square wave frequency output f sqr f pca 2 pca0 cphn --------------------- ------------------- - = note: a value of 0x00 in the pca0cphn regi ster is equal to 256 for this equation. where f pca is the frequency of the clock selected by the cps2?0 bits in the pca mode register, pca0md. the lower byte of the capture/compare module is compared to the pca0 counter low byte; on a match, cexn is toggled and the offset held in the hi gh byte is added to the matched value in pca0cpln. frequency output mode is enabled by setting the ecomn, togn, and pwmn bits in the pca0cpmn reg - ister. important note about capture/compare registers : wh en writing a 16-bit value to the pca0 capture/ compare registers, the low byte should always be wri tten first. writing to pca0cpln clears the ecomn bit to ?0?; writing to pca0 cphn sets ecomn to ?1?. 8-bit comparator pca0l enable pca timebase 000 0 match pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n 0 pca0cphn 8-bit adder pca0cpln adder enable cexn crossbar port i/o toggle 0 1 togn 1 figure 22.7. pca frequency output mode rev. 1.0 271 c8051f360/1/2/3/4/5/6/7/8/9 22.2.5. 8-bit pulse width modulator mode each module can be used independently to generate pulse width modulated (pwm) outputs on its associ - ated cexn pin. the frequency of th e o utput is dependent on the timebase for the pca0 counter/timer. the duty cycle of the pwm output signal is varied using the module's pca0cpln capture/compare register. when the value in the low byte of the pca0 counter /timer (pca0l) is equal to the value in pca0cpln, the output on the cexn pin will be high . when the count value in pca0l ov erflows, the cexn output will be low (see figure 22.8 ). also, when the counter/timer low byte (pca0l) overflows from 0xff to 0x00, pca0cpln is reloaded automatically with the value stor ed in the counter/timer's high byte (pca0h) with - out software intervention. setting the ecomn and pw mn bits in the pca0cpmn register enables 8-bit pulse width modulator mode. the duty cycle for 8-bit pwm mode is given by equation 22.2 . dutycycle 256 pca0 cphn ? () 256 ----------------------------------- ---------------- = equation 22.2. 8-bit pwm duty cycle using equation 22.2, the largest duty cycle is 100% (pca0c ph n = 0), and the smallest duty cycle is 0.39% (pca0cphn = 0xff). a 0% duty cycle may be g enerated by clearing the ecomn bit to ?0?. important note about capture/compare registers : wh en writing a 16-bit value to the pca0 capture/ compare registers, the low byte should always be wri tten first. writing to pca0cpln clears the ecomn bit to ?0?; writing to pca0 cphn sets ecomn to ?1?. 8-bit comparator pca0l pca0cpln pca0cphn cexn crossbar port i/o enable overflow pca timebase 0000 0 q q set clr s r match pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n 0 figure 22.8. pca 8-bi t pwm mode diagram c8051f360/1/2/3/4/5/6/7/8/9 272 rev. 1.0 22.2.6. 16-bit pulse width modulator mode each pca0 module may also be operated in 16-bit pwm mode. in this mode, the 16-bit capture/compare module defines the number of pca0 clocks for the lo w time of the pwm signal. when the pca0 counter matches the module contents, the output on cexn is as serted high; when the counter overflows, cexn is asserted low. to output a varying duty cycle, new value writes should be sy nchronized with pca0 ccfn match interrupts. 16-bit pwm mode is enabled by setting the ecomn, pwmn, and pwm16n bits in the pca0cpmn register. for a varying duty cycle, ccfn shou ld also be set to logic ?1? to enable match inter - rupts. the duty cycle for 16-bit pwm mode is given by equation 22.3 . important note about capture/compare registers : wh en writing a 16-bit value to the pca0 capture/ compare registers, the low byte should always be wri tten first. writing to pca0cpln clears the ecomn bit to ?0?; writing to pca0 cphn sets ecomn to ?1?. equation 22.3. 16-bit pwm duty cycle dutycycle 65536 pca0 cpn ? () 65536 ---------------------------------------------------- - = using equation 22.3, the largest duty cycle is 100% (pca0c pn = 0) , and the smallest duty cycle is 0.0015% (pca0cpn = 0xffff). a 0% duty cycle may be generated by clearing the ecomn bit to ?0?. pca0cpln pca0cphn enable pca timebase 0000 0 pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n 1 16-bit comparator cexn crossbar port i/o overflow q q set clr s r match pca0h pca0l figure 22.9. pca 16-bit pwm mode 22.3. watchdog timer mode a programmable watchdog timer (wdt) func tion is available through the pca module 5. the wdt is used to ge nerate a reset if the time between writes to th e wdt update register (pca0cph5) exceed a specified limit. the wdt can be configured and enabled/disabled as needed by software. with the wdte bit set in the pca0md register, module 5 operates as a watchdog timer (wdt). the mo dule 5 high byte is compared to the pca counter high byte; the module 5 low byte holds the offset to be us ed when wdt updates are performed. the watchdog timer is enabled on reset. writes to some pca registers are restricted while the watchdog timer is enabled. rev. 1.0 273 c8051f360/1/2/3/4/5/6/7/8/9 22.3.1. watchdog timer operation while the wdt is enabled: ? pca counter is forced on. ? writes to pca0l and pca0h are not allowed. ? pca clock source bits (cps2-cps0) are frozen. ? pca idle control bi t ( cidl) is frozen. ? module 5 is forced into software timer mode. ? writes to the module 5 mode register (pca0cpm5) are disabled. while the wdt is enabled, writes to the cr bit will not c hange the pca counter state; the counter will run until the wdt is disabled. the pca co unter run co ntrol (cr) will read zero if the wdt is enabled but user software has not enabled the pca counter. if a ma tch occurs between pca0cph5 and pca0h while the wdt is enabled, a reset will be gener ated. to prevent a wdt reset, the wdt may be updated with a write of any value to pca0cph5. upon a pca0cph5 write, pca0h plus the offset held in pca0cpl5 is loaded into pca0cph5 (see figure 22.10 ). pca0h enable pca0l overflow reset pca0cpl5 8-bit adder pca0cph5 adder enable pca0md c i d l w d t e e c f c p s 1 c p s 0 w d l c k c p s 2 match write to pca0cph5 8-bit comparator figure 22.10. pca module 5 wi th watchdog timer enabled c8051f360/1/2/3/4/5/6/7/8/9 274 rev. 1.0 note that the 8-bit offset held in pca0cph5 is comp ared to the upper byte of the 16-bit pca counter. this offset value is the number of pca0l overflows before a reset. up to 256 pca clocks may pass before the first pca0l overflow occurs, depending on the valu e of the pca0l when the update is performed. the total offset is then given (in pca clocks) by equation 22.4 , where pca0l is the value of the pca0l register at the time of the update. equation 22.4. watchdog time r offset in pca clocks offset 256 pca0 cpl 5 () 256 pca0 l ? () + = the wdt reset is generated when pca0l overflow s while there is a match between pca0cph5 and pca0h. software may force a wdt reset by writing a ?1? to the ccf5 flag (pca0cn.5) while the wdt is enabled. 22.3.2. watchdog timer usage to configure the wdt, perform the following tasks: ? disable the wdt by writing a ?0? to the wdte bit. ? select the desired pca clock s our ce (with the cps2-cps0 bits). ? load pca0cpl5 with the desi r ed wdt update offset value. ? configure the pca idle mode (set cidl if the wdt should be suspended while the cpu is in idle mode). ? enable the wdt by setting the wdte bit to ?1?. ? write a value to pca0cph5 to reload the wdt. the pca clock source and idle mode select cannot be changed while the wdt is enabled. the watchdog time r is enabled by setting the wdte or wdlck bits in the pca0md register. when wdlck is set, the wdt cannot be disabled until the next system reset. if wdlck is not set, the wdt is disabled by clearing the wdte bit. the wdt is enabled following any rese t. th e pca0 counter clock defaults to the system clock divided by 12, pca0l defaults to 0x00, and pca0cpl5 defaults to 0x00. using equation 22.4 , this results in a wdt timeout interval of 3072 system clock cycles. ta b l e 22.3 lists some example time out interv als for typical system clocks. table 22.3. watchdog timer timeout intervals 1 notes: 1. assumes sysclk/12 as the pca clock source, and a pca0l value of 0x00 at the update time. 2. inte rnal oscillator reset frequency. rev. 1.0 275 c8051f360/1/2/3/4/5/6/7/8/9 system clock (hz) pca0cpl5 timeout interval (ms) 24,500,000 255 32.1 24,500,000 128 16.2 24,500,000 32 4.1 18,432,000 255 42.7 18,432,000 128 21.5 18,432,000 32 5.5 11,059,200 255 71.1 11,059,200 128 35.8 11,059,200 32 9.2 3,062,500 2 255 257 3,062,500 2 128 129.5 3,062,500 2 32 33.1 191,406 255 4109 191,406 128 2070 191,406 32 530 32,000 255 24576 32,000 128 12384 32,000 32 3168 c8051f360/1/2/3/4/5/6/7/8/9 276 rev. 1.0 22.4. register descriptions for pca0 following are detailed descriptions of the special func tion registers related to the operation of pca0. sfr definition 22.1. pca0cn: pca control bit 7: cf: pca counter/timer overflow flag. set by hardware when the pca0 counter/timer overflows from 0xffff to 0x0000. when the counter/timer overflow (cf) interrupt is enabled, setting this bit causes the cpu to vec- tor to the cf interrupt service routine. this bit is not automatically cleared by hardware and must be cleared by software. bit 6: cr: pca0 counter /timer run control. this bit enables/disables the pca0 counter/timer. 0: pca0 counter/timer disabled. 1: pca0 counter/timer enabled. bit 5: ccf5: pca0 module 5 capture/compare flag. this bit is set by hardware when a match or capture occurs. when the ccf interrupt is enabled, setting this bit causes the cpu to vect or to the ccf interrupt service routine. this bit is not automatically cleared by hard ware and must be cleared by software. bit 4: ccf4: pca0 module 4 capture/compare flag. this bit is set by hardware when a match or capture occurs. when the ccf interrupt is enabled, setting this bit causes the cpu to vect or to the ccf interrupt service routine. this bit is not automatically cleared by hard ware and must be cleared by software. bit 3: ccf3: pca0 module 3 capture/compare flag. this bit is set by hardware when a match or capture occurs. when the ccf interrupt is enabled, setting this bit causes the cpu to vect or to the ccf interrupt service routine. this bit is not automatically cleared by hard ware and must be cleared by software. bit 2: ccf2: pca0 module 2 capture/compare flag. this bit is set by hardware when a match or capture occurs. when the ccf interrupt is enabled, setting this bit causes the cpu to vect or to the ccf interrupt service routine. this bit is not automatically cleared by hard ware and must be cleared by software. bit 1: ccf1: pca0 module 1 capture/compare flag. this bit is set by hardware when a match or capture occurs. when the ccf interrupt is enabled, setting this bit causes the cpu to vect or to the ccf interrupt service routine. this bit is not automatically cleared by hard ware and must be cleared by software. bit 0: ccf0: pca0 module 0 capture/compare flag. this bit is set by hardware when a match or capture occurs. when the ccf interrupt is enabled, setting this bit causes the cpu to vect or to the ccf interrupt service routine. this bit is not automatically cleared by hard ware and must be cleared by software. sfr page: sfr address: all pages 0xd8 (bit addressable) r/wr/wr/wr/wr/wr/wr/w r/wreset value cf cr ccf5 ccf4 ccf3 ccf2 ccf1 ccf0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rev. 1.0 277 c8051f360/1/2/3/4/5/6/7/8/9 sfr definition 22.2. pca0md: pca0 mode bit 7: cidl: pca0 counte r/timer idle control. specifies pca0 behavior when cpu is in idle mode. 0: pca0 continues to function normally wh ile the system controlle r is in idle mode. 1: pca0 operation is suspended while the system controller is in idle mode. bit 6: wdte: watchdog timer enable if this bit is set, pca module 5 is used as the watchdog timer. 0: watchdog timer disabled. 1: pca module 5 enabled as watchdog timer. bit 5: wdlck: watchdog timer lock this bit locks/unlocks the watchdog timer en able. when wdlck is set, the watchdog timer may not be disabled until the next system reset. 0: watchdog timer enable unlocked. 1: watchdog timer enable locked. bit 4: unused. read = 0b, write = don't care. bits 3?1: cps2-cps0: pca0 co unter/timer pulse select. these bits select the timebase source for th e pca0 counter bit 0: ecf: pca counter/timer overflow interrupt enable. this bit sets the masking of the pca0 co unter/timer overflow (cf) interrupt. 0: disable the cf interrupt. 1: enable a pca0 counter/timer overflow in terrupt request when cf (pca0cn.7) is set. note: when the wdte bit is set to ?1?, the pca0md regist er cannot be modified. to ch ange the contents of the pca0md register, the watchdog timer must first be disabled. sfr page: sfr address: all pages 0xd9 r/w r/w r/w r/w r/w r/w r/w r/w reset value cidl wdte wdlck ? cps2 cps1 cps0 ecf 01000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 cps2 cps1 cps0 timebase 0 0 0 system clock divided by 12 0 0 1 system clock divided by 4 0 1 0 timer 0 overflow 011 high-to-low transitions on eci (max rate = system clock divided by 4) 1 0 0 system clock 1 0 1 external clock divided by 8 (synchronized with system clock) 1 1 0 reserved 1 1 1 reserved note: external clock divided by 8 is synchronized with the system clock. c8051f360/1/2/3/4/5/6/7/8/9 278 rev. 1.0 sfr definition 22.3. pca0cpmn: pca0 capture/compare mode bit 7: pwm16n: 16-bit pulse width modulation enable this bit selects 16-bit mode when pulse width modulation mode is enabled (pwmn = 1). 0: 8-bit pwm selected. 1: 16-bit pwm selected. bit 6: ecomn: comparator function enable. this bit enables/disables the comp arator function for pca0 module n. 0: disabled. 1: enabled. bit 5: cappn: capture posi tive function enable. this bit enables/disables the positive edge capture for pca0 module n. 0: disabled. 1: enabled. bit 4: capnn: capture negative function enable. this bit enables/disables the negative edge capture for pca0 module n. 0: disabled. 1: enabled. bit 3: matn: match function enable. this bit enables/disables the match function for pca0 module n. when enabled, matches of the pca0 counter with a module's capture/comp are register cause the ccfn bit in pca0md register to be set to logic ?1?. 0: disabled. 1: enabled. bit 2: togn: toggle function enable. this bit enables/disables the toggle function for pca0 module n. when enabled, matches of the pca0 counter with a module's capture/comp are register cause the logic level on the cexn pin to toggle. if the pwmn bit is also set to logic ?1?, the module operates in frequency output mode. 0: disabled. 1: enabled. bit 1: pwmn: pulse width modulation mode enable. this bit enables/disables the pwm function for pca0 module n. when enabled, a pulse width modulated signal is output on the cexn pin. 8-bit pwm is used if pwm16n is logic ?0?; 16-bit mode is used if pwm16n logic ?1?. if th e togn bit is also set, the module operates in frequency output mode. 0: disabled. 1: enabled. bit 0: eccfn: capture/compare flag interrupt enable. this bit sets the masking of the capture/compare flag (ccfn) interrupt. 0: disable ccfn interrupts. 1: enable a capture/compare flag interrupt request when ccfn is set. sfr page: pca0cpm0: all pages, pca0cpm1: all pages, pca0cpm2: all pages, pca0cpm3: all pages, pca0cpm4: all pages, pca0cpm5: all pages sfr address: pca0cpm0: 0xda, pca0cpm1: 0xdb, pca0cpm2: 0xdc, pca0cpm3: 0xdd, pca0 cpm4: 0xde, pca0cpm5: 0xdf r/w r/w r/w r/w r/w r/w r/w r/w reset value pwm16n ecomn cappn capnn mat n togn pwmn eccfn 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rev. 1.0 279 c8051f360/1/2/3/4/5/6/7/8/9 sfr definition 22.4. pca0l: pca0 counter/timer low byte bits 7?0: pca0l: pca0 counter/timer low byte. the pca0l register holds the low byte (l sb) of the 16-bit pca0 counter/timer. sfr page: sfr address: all pages 0xf9 r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr definition 22.5. pca0h: pca0 counter/timer high byte bits 7?0: pca0h: pca0 counter/timer high byte. the pca0h register holds the high byte (msb) of the 16-bit pca0 counter/timer. sfr page: sfr address: all pages 0xfa r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr definition 22.6. pca0cpln: pca0 capt ure module low byte bits 7?0: pca0cpln: pca0 capture module low byte. the pca0cpln register holds the low byte (lsb) of the 16-bit capture module n. sfr page: pca0cpl0: all pages, pca0cpl1: all pages, pca0cpl2: all pages, pca0cpl3 : all pages, pca0cpl4: all pages, pca0cpl5: all pages sfr address: pca0cpl0: 0xfb, pca0cpl1: 0xe9, pca0cpl2: 0xeb, pca0cpl3: 0xed, pca0 cpl4: 0xfd, pca0cpl5: 0xf5 r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 c8051f360/1/2/3/4/5/6/7/8/9 280 rev. 1.0 sfr definition 22.7. pca0cphn: pca0 capture module high byte bits 7?0: pca0cphn: pca0 capture module high byte. the pca0cphn register holds the high byte (msb) of the 16-bit capture module n. sfr page: pca0cph0: all pages, pca0cph1: all pages, pca0cph2: al l pages, pca0cph3: all pages, pca0cph4: all pages, pca0cph5: all pages sfr address: pca0cph0: 0xfc, pca0cph1: 0xea, pca0cph2: 0xec, pca0cph3: 0xee, pca0cph4: 0xfe, pca0cph5: 0xf6 r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rev. 1.0 281 c8051f360/1/2/3/4/5/6/7/8/9 23. revision specific behavior this chapter contains behavioral differences between c8051f36x "rev a" and behavior as stated in the data sheet. these deviations will be resolved in the next revis ion of the device. 23.1. revision identification the lot id code on the top side of the device package can be used for decoding device revision informa - tion. on c8051f36x devices the revision letter is the first letter of the lot id code. figures 23.1, 23.2, and 23.3 show how to find the l ot id code on the top side of the device package. c8051f360 a gnzeb 0642 this first character identifies the silicon revision figure 23.1. device package - tqfp 48 c8051f361 a gnzeb 0642 this first character identifies the silicon revision silabs f362 a gnzeb 0642+ this first character identifies the silicon revision c8051f360/1/2/3/4/5/6/7/8/9 282 rev. 1.0 figure 23.2. device package - lqfp 32 figure 23.3. device package - qfn 28 rev. 1.0 283 c8051f360/1/2/3/4/5/6/7/8/9 23.2. c2d port pin requirements problem the c2d debugging port pin (shared with p4.6 for c8051f360/3 and p3.0 for c8051f361/2/4/5/6/7/8/9) behaves differently on "rev a" devices than specified in the data sheet. on "rev a" devices, a c2d port pin that is pulled low by the as sociated port pin driver will disrupt debug - ging capability. in order to communica te with the device th rough the c2 interface, the value in the port latch associated c2d port pin must be '1'. workaround to workaround this problem, add a strong pull-up resistor to the c2d port pin to ensure the pin will be high unless explicitly driven low. furthermore, the port pin should be left in open-drain mode with a '1' in the appropriate port latch (pnmdout bit = '0', pn bit = '1') when not in use. this will allow the debugging soft - ware to transfer data via the c2d pin as often as possible. this behavior has been corrected on "rev b" of this device. c8051f360/1/2/3/4/5/6/7/8/9 284 rev. 1.0 24. c2 interface c8051f36x devices include an on-chip silicon laboratories 2-wire (c2) debug interfac e to allow flash programming and in-system debugging with the producti on part installed in the end application. the c2 interface uses a clock sig nal (c2ck) and a bi-directional c2 data signal (c2d) to transfer information between the device and a hos t system. see the c2 interface specificat ion for details on the c2 protocol. 24.1. c2 interface registers the following describes the c2 registers necessary to perform flash programming functions through the c2 interface. all c2 registers are accessed through the c2 interface as described in the c2 interface spec - ification. c2 register definition 24.1. c2add: c2 address bits7?0: the c2add register is accessed via the c2 interface to select the ta rget data register for c2 data read and data write commands. reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address description 0x00 selects the device id register for data read instructions (deviceid) 0x01 selects the revision id register for data read instructions (revid) 0x02 selects the c2 flash programming control re gister for data read/write instructions (fpctl) 0xbf selects the c2 flash programming data re gister for data read/write instructions (fpdat) c2 register definition 24.2. deviceid: c2 device id this read-only register returns the 8-bit device id: 0x12. c2 address: 0x00 reset value 00010010 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rev. 1.0 285 c8051f360/1/2/3/4/5/6/7/8/9 c2 register definition 24.3. revid: c2 revision id this read-only register returns the 8-bit revision id: 0x00 (revision a) or 0x01 (revision b). c2 address: 0x01 reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 c2 register definition 24.4. fpctl: c2 flash programming control bits7?0 fpctl: flash programming control register. this register is used to enable flash programmi ng via the c2 interface. to enable c2 flash programming, the following codes must be writte n in order: 0x02, 0x01. note that once c2 flash programming is enabled, a system reset mu st be issued to resume normal operation. c2 address: 0x02 reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 c2 register definition 24.5. fpdat: c2 flash programming data bits7?0: fpdat: c2 flash programming data register. this register is used to pass flash comma nds, addresses, and data during c2 flash accesses. valid commands are listed below. c2 address: 0xb4 reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 code command 0x06 flash block read 0x07 flash block write 0x08 flash page erase 0x03 device erase c8051f360/1/2/3/4/5/6/7/8/9 286 rev. 1.0 24.2. c2 pin sharing the c2 protocol allows the c2 pins to be shared wi th user functions so that in-system debugging and flash programming functions may be performed. this is possible because c2 co mmunication is typically performed when the device is in the halt state, where all on-chip peripherals and user software are stalled. in this halted state, the c2 interface can safely ?borrow? the c2ck (/rst) and c2d (p4.6 on c8051f360/3 devices, p3.0 on c8051f361/2/4/5/6/7/8/9 devices) pins. in most applications , external resistors are required to isolate c2 interface traffic from the user ap plication. a typical isolati on configuration is shown in figure 24.1 . c2d c2ck /reset (a) input (b) output (c) c2 interface master c8051fxxx figure 24.1. typical c2 pin sharing the configuration in figure 24.1 assumes the following: 1. the user input (b) cannot change stat e while the target device is halted. 2. the /rst pin on the target device is used as an input only. additional resistors may be necessary depending on the specific application. rev. 1.0 287 c8051f360/1/2/3/4/5/6/7/8/9 d ocument c hange l ist revision 0.1 to revision 0.2 ? updated specification tables with most recently available characterization data. ? fixed an error with the sys clk specification in ta b l e 3.1, ?global electrical ch aracteristics,? on page 33. ? corrected the name of the pmat bit in sfr definition 10.2. ip: interrupt priority . ? corrected the reset value for sfr definition 22.2. pca0md: pca0 mode . revision 0.2 to revision 1.0 ? updated specification tables with characterization data. ?fixed ta b l e 1.1, ?product selection guide,? on page 19 to reflect the correct number of port i/o pins for the c8051f361/2/4/5. ? updated section ?10. interrupt handler? on page 107 . - added note describing ea change behavior when followed by single cycle instruction. ? updated sfr definition 11.1 - changed the mac0sc (mac0cf.5) bit descripti on to c orrectly refer to the mac0sd bit. ? updated sfr definition 15.2 . - changed the emi0cf description to properly describe the 1k xram boundaries. ? added ta b l e 16.2, ?internal low frequency oscillator electrical characteristics,? on page 172 . ? updated sfr definition 16.9 : - specified that the undefined st ates for plllp3?0 are reserved. ? added ta b l e 19.7 and ta b l e 19.8 on page 233 for uart baud rates when using the pll. ? updated ta b l e 22.1, ?pca timebase input options,? on page 265 : - specified that the undefined st ates of cps2?0 are reserved. ? added revision b to ?revision specific behavior? on page 281 . c8051f360/1/2/3/4/5/6/7/8/9 288 rev. 1.0 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 email: mcuinfo@silabs.com internet: www.silabs.com the information in this document is believed to be accurate in all respects at the time of publ ication but is subject to change without notice. silicon laboratories assumes no re sponsibility for errors and omissions, and disclaims responsibi lity for any consequen ces resulting from the use of information included herein. additi onally, silicon laboratories assumes no responsibility for the fun ction- ing of undescribed features or parameters. silicon laboratories reserves the right to make change s without further notice. sili con laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpos e, nor does silicon laboratories assume any liabi lity arising out of the application or use of any product or circuit, and specifi cally disclaims any and all liability, including without limitation consequential or incident al damages. silicon laboratories product s are not designed, intended, or authorized for use in applications in tended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a si tuation where personal injury or death may occur. should buyer purchase or use silicon laboratories prod ucts for any such unintended or unauthorized application, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders |
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